Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource Allocation

International audienceStream processing applications running on Heterogeneous Multi-Processor Systems on Chips (HMPSoCs) require efficient resource allocation and management, both at compile-time and at runtime. To cope with modern adaptive applications whose behavior can not be exhaustively predicted at compile-time, runtime managers must be able to take resource allocation decisions on-the-fly, with a minimum overhead on application performance. Resource allocation algorithms often rely on an internal modeling of an application. Directed Acyclic Graph (DAGs) are the most commonly used models for capturing control and data dependencies between tasks. DAGs are notably often used as an intermediate representation for deploying applications modeled with a dataflow Model of Computation (MoC) on HMPSoCs. Building such intermediate representation at runtime for massively parallel applications is costly both in terms of computation and memory overhead. In this paper, an intermediate representation of DAGs for resource allocation is presented. This new representation shows improved performance for run-time analysis of dataflow graphs with less overhead in both computation time and memory footprint. The performances of the proposed representation are evaluated on a set of computer vision and machine learning applications

Avaliação e testes de heurísticas para otimização de sistemas digitais

This work was developed to interact through an intermediate code, with a framework of synthesis of electronic systems in high level of abstraction in order to optimize combina tional circuits. The framework can be classified as a CAD (Computer Assisted Design) tool that interprets optimizes and translates digital circuits represented in schematic di agram for hardware description language representation. This work works exclusively in the part of refinement where a Genetic Algorithm implementation is used, focusing on the minimization of circuits considering its cost of production. For the development of the Algorithm, we used implementation techniques and test cases adopted from other works, such as parity and comparator function. The results were compared with the objective of evaluating the efficiency of the Algorithm also in relation to the results obtained by two traditional methods of the bibliography that use boolean algebra for minimization, which are Karnaugh and Quine-McCluskey maps. The Genetic Algorithm was effective in most of the test cases and the main disadvantage of this approach was the poor temporal performance.Este trabalho foi elaborado para interagir através de um código intermediário, com um framework de síntese de sistemas eletrônicos em alto nível de abstração a fim de otimizar circuitos combinacionais. O framework pode ser classificado como uma ferramenta CAD (Computer Aided Design) que interpreta otimiza e traduz circuitos digitais representados em diagrama esquemático para a representação em linguagem de descrição de hardware. Este trabalho em específico atua exclusivamente na parte de refinamento onde utiliza-se de uma implementação de Algoritmo Genético tendo enfoque na minimização de circuitos considerando seu custo de produção. Para o desenvolvimento do Algoritmo foram utilizadas t´técnicas de implementação e casos de testes adotados de outros trabalhos como a função paridade ´ımpar e comparador. Os resultados foram comparados com o objetivo de avaliar a eficiência do Algoritmo também em relação aos resultados obtidos por dois m´métodos tradicionais da bibliografia que utilizam da álgebra booleana para a minimização são eles, mapa de Karnaugh e Quine-McCluskey. O Algoritmo Genético foi eficaz na maioria dos casos de testes e destacou-se como principal desvantagem desta abordagem, o fraco desempenho temporal

System-level design of energy-efficient sensor-based human activity recognition systems: a model-based approach

This thesis contributes an evaluation of state-of-the-art dataflow models of computation regarding their suitability for a model-based design and analysis of human activity recognition systems, in terms of expressiveness and analyzability, as well as model accuracy. Different aspects of state-of-the-art human activity recognition systems have been modeled and analyzed. Based on existing methods, novel analysis approaches have been developed to acquire extra-functional properties like processor utilization, data communication rates, and finally energy consumption of the system

Schedule-Extended Synchronous Dataflow Graphs

Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties like throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order schedules. The only generally applicable technique to model a static-order schedule in an SDFG is to convert it to a homogeneous SDFG (HSDFG). This may lead to an exponential increase in the size of the graph and to sub-optimal analysis results (e.g., for buffer sizes in multi-processors). We present techniques to model two types of static-order schedules, i.e., periodic schedules and periodic single appearance schedules, directly in an SDFG. Experiments show that both techniques produce more compact graphs compared to the technique that relies on a conversion to an HSDFG. This results in reduced analysis times for performance properties and tighter resource requirements