UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Physics based modeling of multiple gate transistors on Silicon-on-Insulator (SOI)

G⁴FET is a novel device built on Silicon-on-Isulator (SOI). Due to the presence of Bulk-Si, it is impossible to have more than one gate for each transistor in conventional process technology. However, it is possible to have multiple gates for each transistor in SOI devices due to the presence of buried oxide, which can be used as an independent gate. Besides the oxide gates, junction gates can also be introduced. Due to the presence of the thin active layer, the junction gate can reach to the bottom and can be used to isolate and control the conduction in the transistors. As a result, the maximum number of gates that can be achieved in SOI is four. A transistor with four gates is called G⁴FET. G⁴FET offers all the features of SOI technology. It offers remedies of the drawbacks of Bulk-Si technology. The operation of the multiple gates has applications for mixed-signal circuits, quantum wire, and single transistor multiple gates logic schemes, etc. The research goal is to understand the device physics of G⁴FET. Understanding device physics will provide enough information to set device parameters to optimize device performances. The operation of semiconductor devices depends on several material parameters, device dimensions and structure. The objective of this research is to develop a model that includes material parameters, device dimensions and structure. The second objective of this research is to develop a numerical model from available data. The numerical model is useful for circuit simulation of G⁴FET, which provides information about the characteristics of G⁴FET, when used as a circuit element

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions

Complementary Bodydriving - A Low-voltage Analog Circuit Technique Realized In 0.35um SOI Process

This thesis presents a study of several analog circuit primitives that utilize the body terminal as a signal port to achieve low-voltage operation and high performance. Several issues relating to low-voltage applications as well as the trends of technology scaling in the near future are presented. Principles of the body-driven transistor for both PMOS and NMOS in PDSOI technology are described, and critical design considerations are discussed. The design of low-voltage analog primitives (cascode current mirror and differential pair) are described and analyzed in detail. A discussion of the design and analysis of a 4-quadrant analog multiplier is also presented. Prototyping and testing procedures are discussed and the results of the prototyped circuits are evaluated. Finally, a summary of the work is presented along with insights gained toward future research

Quad configuration for improved thermal design of cascode current mirror

In this paper, the influence of a temperature gradient on the performance of a current mirror will be investigated. It will be proved that a new design based on a quad layout can make the current mirror almost insensitive to a temperature gradient