Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs. Ultra thin body (UTB) SOI MOSFETs are expected to replace conventional MOSFETs for integrated memory applications due to superior electrostatic integrity and better resistant to some of the sources of intrinsic parameter fluctuations. To fully realise the performance benefits of UTB SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into the compact model is developed. The impact on 6T SRAM static noise margin characteristics of discrete random dopants in the source/drain regions and body-thickness variations has been investigated for well scaled devices with physical channel length in the range of 10nm to 5nm. A comparison with the behaviour of a 6T SRAM based on a conventional 35nm MOSFET is also presented

Asenov, A.

Brown, A.R.

Cheng, B.

Roy, S.

Samsudin, K.

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UTB SOI SRAM Cell Stability under theInﬂuence of Intrinsic Parameter FluctuationK. Samsudin , B. Cheng, A. R. Brown, S. Roy and A. AsenovDevice Modelling Group,Dept. of Electronics and Electrical Engineering.University of Glasgow, Glasgow G12 8LT, UK.K.Samsudin@elec.gla.ac.ukAbstract:Intrinsic parameter ﬂuctuations steadily increases withCMOS technology scaling. Around the 90nm technol-ogy node, such ﬂuctuations will eliminate much of theavailable noise margin in SRAM based on conventionalMOSFETs. Ultra Thin Body (UTB) SOI MOSFETs areexpected to replace conventional MOSFETs for integratedmemory applications due to superior electrostatic integrityand better resistant to some of the sources of intrinsicparameter ﬂuctuations. To fully realise the performancebeneﬁts of UTB SOI based SRAM cells a statistical circuitsimulation methodology which can fully capture intrinsicparameter ﬂuctuation information into the compact modelis developed. The impact on 6T SRAM static noisemargin characteristics of discrete random dopants in thesource/drain regions and body-thickness variations hasbeen investigated for well scaled devices with physicalchannel length in the range of 10nm to 5nm. A com-parison with the behaviour of a 6T SRAM based on aconventional 35nm MOSFET is also presented.1. IntroductionUltra Thin Body (UTB) SOI MOSFETs have superiorelectrostatic integrity compared to conventional MOS-FETs. The signiﬁcant reduction in junction capacitance ofSOI MOSFETs also reduces a major component of bitlinecapacitance, which is a critical parameter limiting SRAMperformance [1]. Furthermore a steeper subthresholdslope permits trade off between power consumption andperformance for SRAM cell design.Working UTB MOSFETs with a channel length of 6nmhave already been successfully demonstrated [2]. WhileUTB device can operate without dopant within the chan-nel region there are necessarily discrete random dopantsin the source/drain regions. At nanoscale dimensionsthe discreteness and randomness of the dopants in thesource/drain regions will introduce ﬂuctuations in the ef-fective channel length and access resistance. Additionally,surface roughness at the top and bottom of the Si/SiO2interface will also introduce appreciable local variationsin silicon body thickness and further contribute to devicecharacteristic mismatch. Although UTB devices are thepotential solution to the ultimate MOSFET scaling, an in-depth investigation of UTB MOSFET circuit behaviourin the presence of intrinsic ﬂuctuations is important tounderstand the sources that have greatest contribution toFig. 1: Schematic view of the UTB SOI MOSFETsimulated in this work.Channel Length (nm) 10 7.5 5Gate Oxide Thickness, Tox (nm) 0.67 0.5 0.33Body Thickness, Tsi(nm) 2.5 2.25 2.0Buried Oxide Thickness, Tbox(nm) 50Channel Doping, Na (cm-3) 1e14source-drain Doping, Ns/d (cm-3) 2e20Table 1: Generic device parameters considered.device mismatch that will affect UTB SOI circuit robust-ness and performance. Accurate mismatch modelling isalso necessary to avoid yield loss and overdesign.In this paper a comprehensive statistical device circuitsimulation methodology is used to assess the impact ofthe scaling limit on ﬂuctuation sensitive 6T SRAMs dueto discrete random dopants in the source/drain regionsof UTB SOI MOSFETs. The methodology also helpsto identify key areas for device mismatch optimisationbased on future technology trends. Frequently used inintegrated systems, SRAM cells have a minimum footprint to achieve high integration density. They willbe adversely affected by intrinsic parameter ﬂuctuationsbetween their macroscopically identical transistors, thatsteadily increases with the scaling [3]. A comparison withparameter ﬂuctuation due to body thickness ﬂuctuations[4] and random dopant induced parameter ﬂuctuations inthe channel region of conventional 35nm channel lengthbulk MOSFETs [5] corresponding to current 90nm nodeis also presented.2. UTB SOI Structure and SimulationThe generic structure of the simulated devices is illustratedin Fig. 1 and the corresponding carefully scaled deviceparameters are summarised in Table 1.In order to capture statistical variation in the deviceparameters associated with the discrete random dopantsin the source and drain regions, an ensemble of 200macroscopically identical, but microscopically differentProceedings of ESSDERC, Grenoble, France, 20050-7803-9205-1/05/$20.00 ©2005 IEEE Paper 8.B.2553Fig. 2: Location of discrete random dopants in the sourceand drain regions and variation of effective channel lengthin the silicon body of a 10nm UTB SOI MOSFET.8070605040302010 5  7.5  10V T[mV]Channel Length, L[nm]Body thickness variationDiscrete ’atomistic’ dopingFig. 3: Threshold voltage ﬂuctuations ( VT) in 10nmto 5nm UTB SOI MOSFETs from statistical simulationsof an ensemble of 200 devices with different sources ofintrinsic parameter ﬂuctuation. The threshold voltage isapproximately 200mV.devices is created and simulated using the Glasgow 3D’atomistic’ drift diffusion simulator [6]. The simulatorincludes density gradient quantum corrections which takeinto account the thin-body conﬁnement effects. Theindividual dopants are introduced in the simulation usinga rejection technique describe in [7]. Fig. 2 illustrates thelocation of the discrete random dopants in the source/drainregions and corresponding variation of effective channellength in the silicon body of a 10nm channel length UTBSOI MOSFET.As shown in Fig. 3, the random source/drain dopantsintroduce threshold voltage ﬂuctuations, with a standarddeviation ( VT) increasing from 14mV to 74mV as thedevice is scaled from 10nm to 5nm. It is also evidentthat discrete ’atomistic’ doping in the source/drain regionswill become a dominant source of intrinsic parameterﬂuctuation in UTB SOI devices compared to parameterﬂuctuation due to body thickness variation.3. Statistical Circuit SimulationAn improved two-stage statistical parameter extractionmethodology [4] is employed to capture all device ﬂuc-tuation information obtained from the 3D ’atomistic’ sim-ulator into a representative set of BSIMSOI-FD compactmodels using AuroraTM. In principle, BSIMSOI-FDis ﬂexible enough to describe device mismatch causedby ’atomistic’ ﬂuctuation using a number of carefullychoosen empirical parameters originally introduced tomodel device performance variation caused by differentfoundry processes. Our statistical circuit strategy assureaccurate description limited only by the nature of collected10-810-710-610-510-410-310-2 0  0.1  0.2  0.3  0.4  0.5  0.6  0.7  0.8Log I D (A/m)VG (V)VD = 0.05VVD = [0.8,0.7,0.7]VChannel Length10nm BSIMSOI10nm classical7.5nm BSIMSOI7.5nm classical5nm BSIMSOI5nm classical 0 2 4 6 0  0.4  0.8I D (mA/m)VD (V)Fig. 4: Compact model calibration of gate characteristicsfor all channel lengths and drain characteristics for 10nmchannel length. All characteristics are from nMOSFETUTB SOI.data, whether from simulation or experiment. If used atan early stage of design cycle this methodology couldminimize memory failure probability by statistical sizingof SRAM cell. Statistical circuit simulation based on prin-ciple component analysis (PCA) or backgate propagationof variance (BPV) [8] may not capture all physical ﬂuctu-ation information and may produce misleading results.Firstly, a number of key BSIMSOI model parameters areextracted from the I-V characteristics of generic deviceswith uniform source/drain doping using locally optimised,single device extraction strategy which is a modiﬁcationto the extraction strategy used in partially-depleted de-vices [9]. Figure 4 illustrates the quality of BSIMSOIextraction in respect of the physically simulated ID-VGcharacteristics of 10nm, 7.5nm and 5nm channel lengthsdevices. Results for the ID-VD characteristic ﬁt qualityfor the 10nm transistor are shown in the inset of the sameﬁgure.Parameters which are insensitive to intrinsic ﬂuctuationsare ﬁxed after this phase while seven BSIMSOI pa-rameters are selected for extraction in the second-stage,to represent the variations in characteristics due to therandom dopants in the source/drain regions. The secondphase of extraction consists of two steps. The ﬁrst is basedon the IDVG characteristics at low drain bias, matchingthreshold voltage and sub-threshold slope using Rdsw,Prwg, Nfactor and V off parameters. Then the saturationregion is matched at high drain bias using A1, A2 and Dsubparameters.In BSIMSOI-FD, Rdsw characterizes the access resistancewhile Prwg is the gate-bias effect coefﬁcient of Rdsw.These two parameters can reﬂect effective channel lengthvariation and access resistance ﬂuctuation in the stronginversion region. In the case of body thickness ﬂuctuation,Rdsw is not required and Prwg will reﬂect threshold voltageﬂuctuation in the subthreshold region. Parameter Nfactor isan ideality factor improving the subthreshold descriptionand accommodating different device geometries undervarious conditions, while parameter V off, the offset volt-age in subthreshold region, can be effectively used toreﬂect threshold voltage ﬂuctuation caused by ’atomistic’ﬂuctuation. Parameters A1 and A2 are non-saturationfactors that ultimately determine saturation voltage, there-fore can be used to map random dopant induced elec-Proceedings of ESSDERC, Grenoble, France, 2005554σσ(a) (b)Fig. 5: (a) Circuit schematic of the 6T SRAM. (b) Statictransfer characteristics of 200 statistical SRAM cellsutilising 10nm UTB MOSFET and 35nm bulk MOSFET.tric ﬁeld ﬂuctuations in the pinch-off region. Dsub isthe channel length dependence of drain-induced barrier-lowering (DIBL) effects on threshold voltage and can beused to reﬂect ’atomistic’ ﬂuctuation caused DIBL effectsvariation.The mean RMS errors of the statistical compact modelextraction from all channel lengths are less then 5%percent for each source of intrinsic parameter ﬂuctuationand have a narrow normal distribution for the ensemblesof 200 microscopically different devices. The low RMSerror clearly prove that the choice of seven key parametersadequately describes the effect of discrete random dopantsin the source/drain regions over the whole range of deviceoperation for all samples of devices with channel lengthof 10nm, 7.5nm and 5nm. Worth noting is that the RMSerror for the whole sample of transistors with a particularchannel length depends on the accuracy of the uniformdevice parameter extraction during the ﬁrst stage andcould be improved by improving the extraction strategy.The statistical compact model library built during thisstage are used in Spice simulations. We assume thatboth NMOS and PMOS devices have a similar statisticaldistribution due to random dopant in source-drain region,with PMOS drive half that of NMOS.4. SNM Fluctuation due to intrinsic param-eter ﬂuctuationsA schematic of the 6T SRAM cells simulated for 10nm,7.5nm and 5nm channel length technology with 0.8V,0.7V and 0.7V supply voltage respectively is shown inFig. 5(a). In SRAM cell design the stability of thecell is a critical factor to obtain the desired yield. TheStatic Noise Margin (SNM) [10] which is the minimumDC noise voltage needed to ﬂip the cell state is oftenused to measure the cell’s stability . The stability istypically assessed during the read operation when SRAMis vulnerable to noise. SRAM stability could be improvedby increasing the cell ratio, deﬁned as the ratio of M2,M4 driver transistors width/length (W/L) ratio to the M5,M6 access transistors W/L ratio. This however would alsoincrease the overall cell size. Static transfer curves foran ensemble of 200 10nm channel length UTB MOSFETswith cell ratio 1, considering only discrete random dopingin the source/drain regions, is shown in Fig. 5(b). Thebutterﬂy opening of the transfer curves can be clearly seencompared to the results obtained for 35nm conventionalbulk MOSFET [5]. The bulk MOSFET performance, withthe same cell ratio conﬁguration, is worst due to the largerﬂuctuations resulting from discrete random doping in thechannel region.Fig. 6: SNM distributions for 10nm, 7.5nm and 5nmchannel lengths UTB MOSFETs caused by randomdopants in the source/drain regions.Figure 6 illustrates the distribution of the SNM due todiscrete random doping for SRAM cells based on UTBdevices with different cell ratios, for each channel lengthbeing investigated here. It clearly follows the expectedtrend that increasing cell ratio improves cell stability forall channel lengths reﬂected in the reduced normalizedstandard deviation in Fig. 7. Larger W/L ratios also reducethe magnitude of ﬂuctuations caused by body thicknessvariation, which is partly reﬂected in the normalised stan-dard deviation of SNM. It is also evident that increasingthe cell ratio delivers less improvement of the SNM withdecreasing channel length. For example, in the case ofintrinsic ﬂuctuation caused by discrete random dopants,a cell ratio of 3 gives approximately 60% reduction ofSNM normalised standard deviation for 10nm while only30% reduction for 5nm channel length device. Althoughthere is no extreme SNM deviation for 10nm and 7.5nmUTB SOI MOSFETs device due to random dopants inFig. 7 and body thickness variation in the inset of thesame ﬁgure, the normalised standard deviation of 5nmchannel length device doubles due to ﬂuctuations causedby random dopants in the source/drain regions. For 5nmdevice, resorting to a higher cell ratio would only increasethe cell area, without the full beneﬁt of SRAM scalingcompared to 10nm and 7.5nm channel lengthCalculated from 200 statistical SRAM cell simula-tions for 10nm and 7.5nm UTB SOI MOSFETs and 35nmbulk MOSFET [5] as a function of cell ratio is shown inFig. 8. Note that the UTB devices are only simulated froma cell ratio of 1 to 3 while bulk MOSFET are simulatedfrom a cell ratio of 2 to 4. Fig. 8 depicts the inﬂuenceof intrinsic ﬂuctuations caused by random dopants inthe source/drain regions and body thickness variation inUTB SOI devices, while the conventional MOSFET onlyconsider discrete random doping in channel region. Asapparent from Fig. 8, increasing cell ratio leads toProceedings of ESSDERC, Grenoble, France, 2005555m-6σ 0 10 20 30 40 50 60 70 5  7.5  10SNM: /[%]Channel Length, L[nm]Random dopantCell Ratio1/12/13/1 0 10 20 30 5  7.5  10SNM: /[%]Channel Length, L[nm]Body thicknessFig. 7: Normalised standard deviation of SNM fordifferent channel lengths and cell ratios due to differentsources of intrinsic parameter ﬂuctuations.100806040200 1  2  3  4SNM: -6[mV]Cell RatioCell RatioSOI 10nmSOI 7.5nmBulk 35nmSOI source-drain random dopingSOI body thickness variationBulk channel random dopingFig. 8: of Static Noise Margin (SNM) as a functionof cell ratio for 10nm and 7.5nm UTB SOI MOSFETand 35nm bulk MOSFET. Lines: >32mV for 10nm,>28mV for 7.5nm and >48mV for 35nm.improvement in which implies that a larger fractionof SRAM cells for each geometry become more stable.As a guideline, is required to exceed 4% of thesupply voltage to achieve 90% yield on 1Mbit SRAM’s[11]. This translates to at least a cell ratio of 1 and 2for 10nm and 7.5nm respectively considering only bodythickness variation. If mismatch caused by random dopingis taken into account, a cell ratio of 2 for 10nm and cellratio of 3 for 7.5nm is required. From the SNM point ofview this implies that 6T SRAMs may not gain the fullbeneﬁts from further UTB MOSFET scaling to channellengths smaller than 10nm.Compared to UTB MOSFET based SRAMs, bulk 35nmMOSFETs could not operate at a cell ratio of 1 and requireratio of at least 3, considering only intrinsic ﬂuctuationscaused by discrete random doping effects in the channelregion. In terms of SNM stability, 10nm UTB SOIMOSFETs is suited to replace bulk MOSFETs in SRAMcells as shown in Fig. 8. 10nm UTB device SRAM cellsare more stable even though operated at 80% of the supplyvoltage of 35nm bulk MOSFETs.5. ConclusionsUsing statistical circuit simulation methodology, we havecompared the impact of effective channel length variationand access resistance ﬂuctuation introduced by discreterandom dopants in the source/drain regions with body-thickness ﬂuctuation introduce by interface roughness onthe operation of 6T SRAMs. Simulation results showrandom dopants in source/drain region will become amajor source of device mismatch in UTB SOI MOSFETsbelow the 10nm channel length margin. We have shownthat the operation of 6T SRAM cells based on 10nm UTBSOI MOSFETs is more stable than cells based on 35nmbulk MOSFETs from static noise margin point of view.This could extend the beneﬁts of SRAM scaling beyondthe 25nm technology node [12]. However, novel devicearchitectures such as Double Gate MOSFETs are requiredafter the 10nm channel length mark. It is important thateach potential source of intrinsic parameter ﬂuctuation iscarefully studied in new devices to fully map their impacton the corresponding SRAM cell generations.References:[1] J. B. Kuang, S. Ratanphanyarat, et al., “SRAM bit-line circuits on PD SOI: Advantages and concerns,”IEEE Journal of Solid-State Circuits, vol. 32, June1997.[2] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, and R. A.Roy, “Extreme scaling with ultra-thin Si channelMOSFETs,” in Proc. IEDM, pp. 267–270, IEEE,2002.[3] A. J. Bhavnagarwala, X. Tang, and J. D. Meindl,“The impact of intrinsic device ﬂuctuations onCMOS SRAM cell stability,” IEEE Journal of Solid-State Circuits, vol. 36, April 2001.[4] K. Samsudin, B. Cheng, et al., “Impact of bodythickness ﬂuctuation in nanometre scale UTB SOIMOSFETs on SRAM cell functionality,” in 6thEuropean Conference on Ultimate Integration ofSilicon, (Bologna, Italy), pp. 45–48, April 2005.[5] B. Cheng, S. Roy, and A. Asenov, “The impact ofrandom doping effects on CMOS SRAM cell,” inESSCIRC, 2004.[6] A. R. Brown, F. Adamu-Lema, and A. Asenov,“Intrinsic parameter ﬂuctuations in nanometrescale thin-body SOI devices introduced by inter-face roughness,” Superlattices and Microstructures,vol. 34, pp. 283–291, 2003.[7] A. Asenov, A. R. Brown, et al., “Hierarchicalapproach to atomistic 3-d mosfet simulation,”IEEE Transactions on Computer Aided Design ofIntegrated Circuits and Systems, vol. 18, November1999.[8] P. G. Drennan and C. C. McAndrew, “UnderstandingMOSFET mismatch for analog design,” IEEEJournal of Solid-State Circuits, vol. 38, March 2003.[9] P. Su, An International Standard Model for SOICircuit Design. PhD thesis, Electrical Engineeringand Computer Science, University of California,Berkeley, 2002.[10] E. Seevinck, F. List, and J. Lohstroh, “Static-noisemargin analysis of MOS SRAM cells,” IEEE Journalof Solid-State Circuits, vol. 22, October 1987.[11] P. Stolk, H. Tuinhout, et al., “CMOS deviceoptimization for mixed-signal technologies,” Tech.Digest IEDM, pp. 215–218, 2001.[12] “International Technology Roadmap for Semicon-ductors,” 2003.Proceedings of ESSDERC, Grenoble, France, 2005556m-6σm-6σm-6σm-6σ

An International Standard Model for SOI Circuit Design.

CMOS device optimization for mixed-signal technologies,”

Extreme scaling with ultra-thin Si channel MOSFETs,” in

Hierarchical approach to atomistic 3-d mosfet simulation,”

Impact of body thickness ﬂuctuation in nanometre scale

Intrinsic parameter ﬂuctuations in nanometre scale thin-body SOI devices introduced by interface roughness,”

McAndrew,“Understanding MOSFET mismatch for analog design,”

Roadmap for Semiconductors,”

SRAM bitline circuits on PD SOI: Advantages and concerns,”

Static-noise marginanalysisofMOSSRAMcells,”

The impact of intrinsic device ﬂuctuations

The impact of random doping effects on

UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

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UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation

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