Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

Thermal stability analysis and performance exploration of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET for high performance circuit applications

This paper explores the performance of asymmetrical dual-k underlap spacer (ADKUS) SOI FinFET (device-D1) over the wide temperature range (200 K-450 K). An attempt has been made to find out the zero temperature coefficient (ZTC) biased point to enhance the digital, analog and RF performance at 20 nm channel length. The proposed device will be suitable for VLSI circuit’s design, internet of things (IoT) interfacing components and algorithm development for security applications of information technology. The potential parameters of device-D1 like intrinsic gain (AV ), output conductance (gd ), transconductance (gm ), early voltage (VEA ), off current (Ioff) , on current (Ion), Ion/Ioff ratio, gate to source capacitance (Cgs), gate to drain capacitance (Cgd), cut-off frequency (fT), energy (CV2), intrinsic delay (CV/I), energy-delay product (EDP), power dissipation (PD), sub-threshold slope (SS), Q-Factor (gm,max/SS), threshold voltage (Vth) and maximum trans-conductance (gm,max) are subjected to analyze for evaluating the performance of ADKUS SOI FinFET for wide temperature environment. The validation of a temperature based performance of ADKUS SOI FinFET gives an opportunity to design the numerous analog and digital components of internet security infrastructure at wide temperature environment. These ADKUS SOI FinFET based components give new technology to the IoT which has the ability to connect the real world with the digital world and enables the people and machines to know the status of thousands of components simultaneously

3D Device Modeling and Assessment of Triple Gate SOI FinFET for LSTP Applications

The FinFET is a very good candidate for future VLSI due to its simple architecture and better performance when compared to SOI MOSFET. SGOI (Silicon Germanium on Insulator) Recessed Source drain MOSFETs and SOI FinFETs are analyzed by a commercial 3-D device simulator. It is shown that SOI FinFET with Thin Fin widths compared to SGOI MOSFETs Body thicknesses, have better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. By varying the spacer width and the Fin width, device performance is found to improve. The performance of triple gate FinFET has been compared with that of Ultra-Thin Body (UTB) Recessed Source drain SGOI MOSFET in terms of delay, power consumption and noise margin for a CMOS inverter and results indicate the better suitability of SOI FinFET structures for Low standby Power(LSTP) Applications. The SOI FinFET device Sensitivity to process parameters such as Gate Length, Spacer Width, Oxide thickness, Fin Width, Fin Height and Fin doping has been examined and reported

PERFORMANCE COMPARISON OF BULK FINFET WITH SOI FINFET IN NANO-SCALE REGIME

This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also compares the performance improvement of Multi-gate Bulk and SOI MOSFET over Single-gate bulk and SOI MOSFET.The simulation results are obtained with the help of TCAD 3-D device simulator are well matched with the ideal characteristics

3D Simulation of Fin Geometry Influence on Corner Effect in Multifin Dual and Tri-Gate SOI-Finfets

In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate SOI-FinFETs is studied through a commercial, three-dimensional numerical simulator ATLAS from Silvaco International. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. This study aims wider to use multiple fins between the source and drain regions. The results indicate that for both multifin double and triple gate FinFETs, the corner effect does not lead to an additional leakage current and therefore does not deteriorate the SOI-FinFET performance

High Sensitivity Dual-Gate Four-Terminal Magnetic Sensor Compatible with SOI FinFET Technology

This letter presents a unique device concept of split-current magnetic sensor that is fully compatible with SOI FinFET technology. The fabricated dual-gate four-terminal device brings a step change in SOI integrated sensor capabilities, its measured current related relative sensitivity is as high as 3400 % T-1 at 2 μA of total supply current, comparing to the sensitivity of 3%T-1 exhibited by commercially available silicon MagFETSs. The device’s very high sensitivity is attributed to its novel current conduction phenomena and the internal magnetic deflection enhancement loop demonstrated using 3D TCAD numerical simulations. This new magnetic sensor is a very promising candidate for the next generation of magnetic sensitive smart-power integrated circuits

Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability

In this paper we illustrate how by using advanced atomistic TCAD tools the interplay between long-range process variation and short-range statistical variability in FinFETs can be accurately modelled and simulated for the purposes of Design-Technology Co-Optimization (DTCO). The proposed statistical simulation and compact modelling methodology is demonstrated via a comprehensive evaluation of the impact of FinFET variability on SRAM cell stability

PERFORMANCE ANALYSIS AND OPTIMIZATION OF 10 NM TG N- AND P-CHANNEL SOI FINFETS FOR CIRCUIT APPLICATIONS

This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P-channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD with the Bohm quantum potential (BQP) algorithm. The influence of the geometrical parameters on the threshold voltage VTH, the subthreshold swing (SS), the transconductance and the on/off current ratio, ION/IOFF, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P-FinFET can reach a minimum SS value with Fin heights of 15 nm and 9 nm, respectively. In addition, low threshold voltages of 0.61 V and 0.27 V for N- and P-channel SOI FinFETs, respectively, are obtained at a Fin width of 7 nm