The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

Annema, A.J.

Doornbos, G.

Nauta, B.

Veldhorst, P.

English

Annema, Anne J.

Doornbos, G

Nauta, Bram

University of Twente Research Information

332 •  2009 IEEE International Solid-State Circuits ConferenceISSCC 2009 / SESSION 19 / ANALOG TECHNIQUES / 19.619.6 A sub-1V Bandgap Voltage Reference in 32nm FinFET TechnologyA.J. Annema1, P. Veldhorst1, G. Doornbos2, B. Nauta11University of Twente, Enschede, Netherlands2NXP-TSMC Research Center, Leuven, BelgiumThe bulk CMOS technology is expected to scale down to about 32nm node andlikely the successor would be the FinFET. The FinFET is an ultra-thin bodymulti-gate MOS transistor with among other characteristics a much highervoltage gain compared to a conventional bulk MOS transistor [1]. Bandgapreference circuits cannot be directly ported from bulk CMOS technologies toSOI FinFET technologies, because both conventional diodes cannot be realizedin thin SOI layers and also, area-efficient resistors are not readily available inprocesses with only metal(lic) gates. In this paper, a sub-1V bandgap refer-ence circuit is implemented in a 32nm SOI FinFET technology, with an archi-tecture that significantly reduces the required total resistance value.  The conventional CMOS bandgap voltage reference adds a proportional-to-absolute-temperature (PTAT) voltage and a complementary-to-absolute-tem-perature (CTAT) voltage to get a stable output voltage that is approximatelyequal to the material bandgap. The CTAT voltage typically is obtained from aforward-biased diode, e.g., a source-well junction. The resulting referencevoltage in CMOS is then about 1.2V, which does not fit in the supply voltageof today’s deep sub-micron CMOS technologies. In [2] one of the most wide-ly applied approaches to create good sub-1V bandgap reference circuits ispresented and serves as the basis for many circuit implementations, e.g., [3].A disadvantage of the approach in [2] is that it uses a number of matchedhigh-ohmic resistors that take a significant die area for low-power referencecircuits. SOI FinFET-transistors do not have wells, which eliminates the possibility ofusing source-well junctions as diodes. As replacement for the typical source-well junction in bulk CMOS processes, a lubistor [3] structure is implementedwith the poly tied to ground, similar to the work in [4]. The lubistor structureis shown in Fig. 19.6.1; the gate-material layer above the pn-junction shieldsthe junction from silicidation (i.e. prevents shorting the pn-junction) while ann-type background dope ensures that the region below the shield is non-intrinsic. Due to the lateral junction in the thin silicon layer, the area efficiencyis quite low:  structures are designed with 1.4µm pitch having 60nm junctionheight. The dimensions of the diodes in this work, are estimated using 2Dsemiconductor simulations, resulting in a total of 440µm junction-width perunit diode, which corresponds to 440µm×1.4µm/2=308µm2 die area and440µm×60nm=26.4µm2 effective junction area; for circuit simulations of thetotal circuit the FinFET-model in [5] is used. In the SOI FinFET technology used in this work no high resistivity layers areavailable to allow the creation of dedicated resistors: resistors then are area-inefficient and Banba’s approach [2] would result in a large area overhead.Resistorless voltage references in CMOS either show poor accuracy andreproducibility or, are targeted at 1.2V output voltages [6]. Therefore, theapproach in this paper uses two relatively small resistors and resistorlessweighted-averaging to realize area efficient sub-1V bandgap voltage refer-ences, see Fig. 19.6.2. The principle of a conventional bandgap voltage refer-ence can be captured in one relation that describes the voltage-temperature behavior:                                                               .  Here the termis created by the difference voltage across two diodes operated at different current densities, the term                 approximates the diode’s voltage drop as a function of temperature and N includes things like resistor ratios, diodearea ratios, and current-mirror ratios in the circuit. Adding a PTAT and CTATvoltage yields a (in first order) temperature independent output voltage forVref(T)≈1.2V. Noting that, it directly follows that by weighted averaging of a CTAT voltage and a PTATvoltage a temperature independent sub-bandgap output voltage can beobtained. In related work in [7,8] averaging is done using relatively high-ohmic resistors. In this work, matched OTAs are used to replace the highohmic resistors in such a way that OTA non-linearity is cancelled, while thereverse isolation of the OTAs decouples the core of the bandgap reference cir-cuit from the output voltage. The total bandgap voltage reference circuit in Fig.19.6.2 uses two identical OTAs that yields m=2 and hence, an output voltageof about 0.6V. A total of 56kΩ of resistors is used, at 14µA of supply currentat room temperature. Compared to using the Banba approach, this is about 6×less in total resistor value for the same supply-current level.The die micrograph of the FinFET sub-1V bandgap reference is shown in Fig.19.6.3. The total area of the bandgap voltage reference circuit is about100×160µm2. For this design, the total active area can be broken down in 54%diode area, 31% resistor area, and 15% MOS-transistor area. The large diodearea is due to the low area efficiency of lubistor structures in thin-body SOIprocesses. The resistors are implemented as narrow silicided poly lines. Apartfrom this, some of the area inside the 100×160µm2 is unused or means fortesting purposes. Figure 19.6.4 shows the I(V) plots of two different lubistors for various tem-peratures. The left hand side shows typical behavior for the lubistor in the cir-cuit with the highest current density: the leftmost diode in Fig. 19.6.2. Thedots correspond to the typical quiescent point in the bandgap reference cir-cuit, which is a little into the region where the I(V) relation starts to deviatefrom the ideal exponential behavior. The rightmost lubistor in Fig. 19.6.2 hasa 10× lower current density and therefore, operates in the exponential regime.The origin of the bump for the curve at 25°C is unexplained, but located wellbelow the quiescent point. The right hand side of Fig. 19.6.4 shows the I(V)behavior of a misbehaving lubistor, for which, the bump occurs in the operat-ing region, making the bandgap reference circuit dysfunctional. It must benoted that this technology is not released for production and is still in anexperimental phase.Figure 19.6.5 shows the output voltage of the reference as a function of sup-ply voltage for a few samples at room temperature. The circuit operates cor-rectly for supply voltages above 0.9V; the sharp transition in the output volt-age is due to the start-up circuit. Figure 19.6.6 shows the output voltage ofone sample as a function of temperature, at low temperature, the increase inoutput voltage is mainly due to surface leakage currents due to moist; at hightemperature the main cause for the roll-off is the operation into the high-injec-tion region of the lubistor. The measured supply current is 14µA at room tem-perature.Acknowledgement:We thank G. Wienk for his great assistance with the measurements.References:[1] M.J.H. van Dal, N. Collaert, G. Doornbos, et al., “Highly Manufacturable FinFETs withsub-10nm fin Width and High Aspect Ratio Fabricated with Immersion Lithography,”IEEE VLSI Technology Symposium, pp. 110-111, Jun., 2007.[2] H. Banba, H. Shiga, A. Umezawa, et al., “A CMOS Bandgap Reference Circuit withsub-1V Operation,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May, 1999.[3] S. Voldman, R. Schulz, J. Howard, et al., “CMOS-on-SOI ESD Protection Networks,”Electrical Overstress/Electrostatic Discharge Symp., pp. 291-301, Sept., 1996.[4] G. Knoblinger, F. Kuttner, A. Mashall, et al., “Design and Evaluation of Basic AnalogCircuits in an Emerging MuGFET Technology,” IEEE International SOI Conference, pp. 39-40, Oct., 2005.[5] G.D.J. Smit, A.J. Scholten, N. Serra, et al., “PSP-Based Compact FinFET ModelDescribing dc and RF Measurements,” IEDM, pp. 1-4, Dec., 2006.[6] A. Buck, C. McDonald, S. Lewis, T.R. Viswanathan, “CMOS Bandgap Reference with-out Resistors,” ISSCC Dig. Tech. Papers, pp. 442 – 443, Feb., 2000.[7] J. Doyle, Y.-J. Lee, Y.-B. Kim, et al., “A CMOS Subbandgap Reference Circuit with 1-V Power Supply Voltage,” IEEE J. Solid-State Circuits, vol. 39, no. 1,   pp. 252-255, Jan.,2004.[8] E.C. Dijkmans, “Hearing Instruments Go Digital,” European Solid-State Circuits Conf.,pp. 16-28, Sept., 1997.978-1-4244-3457-2/09/$25.00 ©2009 IEEE( ) ⋅−+⋅≈+=⋅−≈+=⇔≈+=333DIGEST OF TECHNICAL PAPERS  •ISSCC 2009 / February 10, 2009 / 3:30 PMFigure 19.6.1: Lubistor structure (used as a pn-junction). Figure 19.6.2: The sub-1V bandgap circuit in a 32nm FinFet technology.Figure 19.6.3: Die micrograph of the bandgap reference circuit in a 32nm FinFET tech-nology, size 100×160µm2.Figure 19.6.5: Output voltage as a function of supply voltage, 3 samples. Figure 19.6.6: Output voltage as a function of temperature, 1 sample.Figure 19.6.4: Lubistor measurement results for a decent lubistor with dots indicatingthe quiescent point in the bandgap reference circuit (left) and a misbehaving lubistor(right). 19

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

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