Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Miniaturization of on-chip passive electronic devices by silicon nitride self-rolled-up membrane microtube nanotechnology

Miniaturization of the commonly used on-chip lumped elements is highly desirable to enhance the density, performance and functionality of integrated circuits (ICs) working from DC to millimeter wave frequency band. Numerous improvement methods have been demonstrated but all fail to fundamentally solve the intrinsic drawbacks of currently used planar spiral platforms for passive lumped elements. A new design platform based on self-rolled-up membrane (S-RuM) nanotechnology that “processes like 2-D and functions like 3-D” is proposed for constructing on-chip three-dimensional (3-D) rolled-up microtube structures. By taking lumped inductors and transformers, this thesis demonstrates a global solution to obtain on-chip lumped elements with an extremely small on-chip footprint and almost complete immunity to substrate issues. The fabrication process of S-RuM lumped elements is designed to be CMOS compatible with a clear trend to achieving 100% fabrication yield. A quasi-dynamic finite element method (FEM) is established to precisely calculate the dimensions of rolled-up structures, which allows an accurate simulation of the electrical performance of S-RuM lumped passive devices by physical modeling. The design of the S-RuM inductor from FEM structural simulation to physical model electrical simulation is demonstrated, and its physical model is further integrated into the commercial Advanced Design System (ADS) software as a design kit for circuit-level simulation. Full wave FEM 3-D modeling of ICs including S-RuM inductors in the layouts is enabled by EMPro and ADS FEM co-simulation. A simple high pass filter is used as an example to show the S-RuM IC design process. A clear trend to save 38% ~ 50% chip size is also shown in active IC examples by replacing planar spiral inductors with S-RuM inductors. As a unit device, the S-RuM inductor can be used to build other passive elements like transformers. So, the S-RuM transformer is also investigated in this thesis. The thermal and mechanical reliability of the S-RuM platform are tested by using rapid thermal annealing (RTA) and nano-indention, which provide data for further packaging S-RuM lumped passive devices and applications in a power electronics. All samples are fabricated on a 1 to 10 cm p-type silicon substrate. Cu based S-RuM inductor samples show a 119 nH/mm2 inductance density, Q factor of 3 @ 8 GHz, a 0.3 nH to 2.4 nH inductance range, a self-resonant-frequency (SRF) of ~20 GHz, 250 C thermal stability, and 48.6 N/m stiffness. Au based S-RuM transformer samples shows a 1.52:1 turn ratio (n), 0.99 mutual magnetic coupling coefficient (km), and 0.392 maximum available gain at 8.6 GHz with a footprint (S) of only ~0.0085 mm2. The corresponding index of transformer performance ((n∙ km)/S ) is 177, which is ~2 than that of the best on-chip planar transformer reported so far with a similar turn ratio. The performance of the S-RuM transformers is stable at temperatures up to 250 ºC, and the hardness of the rolled-up structures is as high as 270.2 N/m

Integrated Antennas and Active Beamformers Technology for mm-Wave Phased-Array Systems

In this thesis, based on the indoor channel measurements and ray-tracing modeling for the indoor mm-wave wireless communications, the challenges of the design of the radio in this band is studied. Considering the recently developed standards such as IEEE 802.15.3c, ECMA and WiGig at 60 GHz, the link budget of the system design for different classes of operation is done and the requirement for the antenna and other RF sections are extracted. Based on radiation characteristics of mm-wave and the fundamental limits of low-cost Silicon technology, it is shown that phased-array is the ultimate solution for the radio and physical layer of the mobile millimeter wave multi-Gb/s wireless networks. Different phased-array configurations are studied and a low-cost single-receiver array architecture with RF phase-shifting is proposed. A systematic approach to the analysis of the overall noise-figure of the proposed architecture is presented and the component technical requirements are derived for the system level specifications. The proposed on-chip antennas and antenna-in-packages for various applications are designed and verified by the measurement results. The design of patch antennas on the low-cost RT/Duroid substrate and the slot antennas on the IPD technologies as well as the compact on-chip slot DRA antenna are explained in the antenna design section. The design of reflective-type phase shifters in CMOS and MEMS technologies is explained. Finally, the design details of two developed 60 GHz integrated phased-arrays in CMOS technology are discussed. Front-end circuit blocks such as LNA, continuous passive reflective-type phase shifters, power combiner and variable gain amplifiers are investigated, designed and developed for a 60 GHz phased-array radio in CMOS technology. In the first design, the two-element CMOS phased-array front-ends based on passive phase shifting architecture is proposed and developed. In the second phased-array, the recently developed on-chip dielectric resonator antenna in our group in lower frequency is scaled and integrated with the front-end

Conception et intégration "above IC" d'inductances à fort coefficient de surtension pour applications de puissance RF

De tous les circuits qui constituent un système radiofréquence complet, la partie radiofréquence apparaît comme un maillon délicat du système. Parmi les nombreuses fonctions radiofréquences, l'amplificateur de puissance (PA) représente un bloc particulièrement critique de la chaîne d'émission, du fait de sa consommation élevée et des forts niveaux des signaux qu'il doit gérer. Il résulte de ces contraintes que les techniques d'intégration utilisées sont généralement complexes et onéreuses, particulièrement pour la réalisation des éléments inductifs des réseaux de pré-adaptation des transistors de puissance, à partir de fils micro-soudés. Les travaux décrits dans ce manuscrit visent ainsi le développement d'une technologie permettant l'intégration faible coût d'inductances planaires de puissance en mesure de remplacer les fils micro-soudés. Ces travaux ont été réalisés en collaboration avec la société Freescale. Les démonstrateurs présentés mettent donc en œuvre la filière LDMOS sur substrat silicium faiblement résistif. Le mémoire est articulé autour de quatre chapitres. Le premier présente un état de l'art de l'intégration des amplificateurs de puissance RF à partir duquel nous définissons la problématique de cette intégration. Dans le deuxième chapitre, nous traitons des différents mécanismes de pertes présents dans les inductances planaires sur silicium ainsi que de leurs origines. Puis, nous posons les bases de leur modélisation électrique et des simulations électromagnétiques 3D qui seront conduites pour leur optimisation. Le troisième chapitre est ensuite consacré à la description et à l'optimisation de la technologie mise en place au sein du LAAS. Elle met en œuvre, sur un plan métallique qui écrante le silicium sur lequel sont intégrés les transistors, une couche de 65 µm de résine époxy SU8 sur laquelle est implémenté un niveau métallique en cuivre de 35 µm d'épaisseur. Des trous métallisés sont aussi réalisés à travers le niveau SU8 pour les contacts électriques entre les transistors et le niveau Cu supérieur. Enfin, le quatrième et dernier chapitre traite des caractérisations expérimentales des inductances de test réalisées ainsi que des démonstrateurs intégrant ces inductances directement sur la puce de puissance LDMOS. Dans ce dernier cas, des mesures en forts signaux sont aussi présentées. L'intégration "Above-IC" d'un réseau d'inductances parallèles présentant une valeur finale de 0.2nH pour un facteur de qualité de 40 à 2 GHz et de 58 à 5 Ghz, tout en supportant une densité de courant de 1A/mm², permet d'aboutir à une valeur du rendement de 60% pour un amplificateur RF LDMOS de puissance 50W.Of all the circuits of a complete radio frequency system, the RF transmission section is still a delicate part of the system. In fact, it is widely known that the RF power amplifier (PA) is one of the most critical building blocks of the transmission chain, because of its high power consumption and high signal levels that it must handle. As a result, integration techniques are generally complex and expensive, particularly for the realization of inductive elements of the power amplifier's impedance pre-matching circuits using bond wires. The aim of the work described in this manuscript is the development of a low cost microelectronic technology for planar power inductor integration which could lead to bond wires replacement. This work was carried out in collaboration with Freescale semiconductor Inc. All demonstrators involve LDMOS dies implemented on weakly resistive silicon substrates. The manuscript is articulated around four chapters. The first one defines integration issues from the presentation of a state of the art of RF power amplifier technologies. In the second chapter, we discuss loss mechanisms present in planar inductors integrated above silicon substrates and their location. Then, we present the equivalent electrical schematic of these inductors as well as 3D electromagnetic simulations conducted for their optimization. The third chapter is then devoted to the description and optimization of the technological process developed in the LAAS/CNRS. The process consists of depositing, above a ground shielded silicon substrate, a 65 µm thick SU8 layer acting as a dielectric for the 35 µm thick copper based inductor. Via holes through the SU8 layer are used to form an electrical connection between the inductor and transistors. The fourth and final chapter deals with experimental characterizations performed on integrated test inductors, as well as on power LDMOS demonstrators realized from the direct inductor above-IC integration on active chips. The integration of parallel inductors with a 0.2 nH final value, having a quality factor of 40 at 2 GHz or 58 at 5 GHz and supporting a current density of 1 A/mm², leads to the realization of a 50W LDMOS RF power amplifier exhibiting a 60% efficiency

NASA Tech Briefs, September 1997

Topics include: Data Acquisition and Analysis; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Software; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences