Custom Integrated Circuits

Contains reports on nine research projects.Analog Devices, Inc.International Business Machines CorporationJoint Services Electronics Program Contract DAAL03-89-C-0001U.S. Air Force - Office of Scientific Research Contract AFOSR 86-0164BDuPont CorporationNational Science Foundation Grant MIP 88-14612U.S. Navy - Office of Naval Research Contract N00014-87-K-0825American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

Testability of Switching Lattices in the Cellular Fault Model

A switching lattice is a two-dimensional array of four-terminal switches implemented in its cells. Each switch is linked to the four neighbors and is connected with them when the switch is ON, or is disconnected when the switch is OFF. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, lattices of multi-terminal switches, originally introduced by Akers in 1972, have found a renewed interest. In this paper, the testability under the Cellular Fault Model (CFM) of switching lattices is defined and analyzed. Moreover, some techniques for improving the testability of lattices are discussed and experimentally evaluated

FPGA technology mapping optimizaion by rewiring algorithms.

Tang Wai Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 40-41).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.iiiChapter 1 --- Introduction --- p.1Chapter 2 --- Rewiring Algorithms --- p.3Chapter 2.1 --- REWIRE --- p.5Chapter 2.2 --- RAMFIRE --- p.7Chapter 2.3 --- GBAW --- p.8Chapter 3 --- FPGA Technology Mapping --- p.11Chapter 3.1 --- Problem Definition --- p.13Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16Chapter 3.2.1 --- FlowMap --- p.16Chapter 3.2.2 --- FlowSYN --- p.21Chapter 3.2.3 --- CutMap --- p.22Chapter 4 --- LUT Minimization by Rewiring --- p.24Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27Chapter 4.2 --- Experimental Result --- p.28Chapter 5 --- Conclusion --- p.38Bibliography --- p.4

Routing, Driven Placement for ATMEL 6000 Architecture FPGAs

Based on the concept of Cell Binary Tree (CBT), a new technique for mapping combination circuits into ATMEL 6000 Architecture FPGAs is presented in this thesis. Cell Binary Tree (CBT) is a net-list representation of combinational circuits. For each node of CBT there is a distinguished variable associated with it, the node itself represents a certain logic function, which is selected according to target FPGA architecture. The proposed CBT placement algorithms preserve local connectivity and allow better mapping into ATMEL FPGA. Experiments reveal that the new mapping technique achieved reduction in a number buses used for routing comparing with previously proposed Modified Squashed Binary Tree (MSBT) approach and possibly reduction of area as well. In general, the new technique is realized through following four major steps: 1. Grouping and generating CBT: This is a step to read blifformat file, which is the result of logic synthesis, into a CBT data structure through grouping algorithm, which is a process of gathering logic functions into nodes for mapping based on a targeted FPGA architecture. The main objective of creating CBT is to generate a minimum number of nodes (or cells) to be mapped. 2. CBT placement: Upon getting the minimum number of nodes in CBT to be mapped, the next step is to map those nodes into cells in FPGA. The significance of the placement method in this thesis is to lineup the cells with the same variable into the same row in the FPGA. 3. Bus Assignment: The process of assigning variables to local buses, which run in two possible directions; horizontal and vertical. ATMEL 6000 has two horizontal buses and two vertical buses for each cell. The assignment is based on the number of times a variable appears in a row or column. 4. Routing: The last stage of the process is the connecting cells which have the same input variable. One of the important steps in the routing process is to choose connection bridge cells with the minimum impact on the area

Area-power-delay trade-off in logic synthesis

This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis system. To achieve this, a new delay model is presented, which gives accurate delay estimations for arbitrary sets of Boolean expressions. This allows use of this delay model already during the very first steps of logic synthesis. Furthermore, new algorithms are presented for a number of different optimization tasks within logic synthesis. There are new algorithms to create prime irredundant Boo lean expressions, to perform technology mapping for use with standard cell generators, and to perform gate sizing. To prove the validity of the presented ideas, benchmark results are given throughout the thesis

Balance of Threat, Balance of Mind: Nuclear Rivalry and Arms Control

Under what conditions will rivals choose to accept mutual constraints, limitations, and even reductions on their capabilities for waging war? Contemporary political science lacks a strong theoretical basis for understanding this behavior, despite the fact that states in the modern era continue to negotiate and enter into arms control arrangements. This study contributes a theoretical framework and empirical analysis identifying the conditions under which nuclear-armed rivals might choose to curb their deadly arsenals. Traditional theories grounded in classical deterrence theory suggest arms control serves to preserve a deterrent status quo and prevent expensive and destabilizing arms competition; it should therefore only be expected when rivals feel secure in the strength and effectiveness of their respective retaliatory capabilities. This study suggests a more complicated (yet still predictive) causal logic in which this balance of force is dynamically interactive with militarized hostility and rivals convergence or divergence in how they think — both normatively and instrumentally — about the role of nuclear weapons in their national security. The argument is illustrated through qualitative comparative analysis (QCA) of bilateral arms control interactions among nuclear-armed strategic rivals from 1949 to the present. Further analysis is provided through in-depth case studies of arms control dynamics between three pairs of contemporary nuclear rivals — the United States and Russia, India and Pakistan, and the United States and China