Synthetic biology and microdevices : a powerful combination

Recent developments demonstrate that the combination of microbiology with micro-and nanoelectronics is a successful approach to develop new miniaturized sensing devices and other technologies. In the last decade, there has been a shift from the optimization of the abiotic components, for example, the chip, to the improvement of the processing capabilities of cells through genetic engineering. The synthetic biology approach will not only give rise to systems with new functionalities, but will also improve the robustness and speed of their response towards applied signals. To this end, the development of new genetic circuits has to be guided by computational design methods that enable to tune and optimize the circuit response. As the successful design of genetic circuits is highly dependent on the quality and reliability of its composing elements, intense characterization of standard biological parts will be crucial for an efficient rational design process in the development of new genetic circuits. Microengineered devices can thereby offer a new analytical approach for the study of complex biological parts and systems. By summarizing the recent techniques in creating new synthetic circuits and in integrating biology with microdevices, this review aims at emphasizing the power of combining synthetic biology with microfluidics and microelectronics

Reliability improvement of electronic circuits based on physical failure mechanisms in components

Traditionally the position of reliability analysis in the design and production process of electronic circuits is a position of reliability verification. A completed design is checked on reliability aspects and either rejected or accepted for production. This paper describes a method to model physical failure mechanisms within components in such a way that they can be used for reliability optimization, not after, but during the early phase of the design process. Furthermore a prototype of a CAD software tool is described, which can highlight components likely to fail and automatically adjust circuit parameters to improve product reliability

Expanding Rapid Prototyping for Electronic Systems Integration of Arbitrary Form

An innovative method for rapid prototyping (RP) of electronic circuits with components characteristic of typical electronics applications was demonstrated using an enhanced version of a previously developed hybrid stereolithography (SL) and direct write (DW) system, where an existing SL machine was integrated with a three-axis DW fluid dispensing system for combined arbitrary form electronic systems manufacturing. This paper presents initial efforts at embedding functional electronic circuits using the hybrid SL/DW system. A simple temperature-sensitive circuit was selected, which oscillated an LED at a frequency proportional to the temperature sensed by the thermistor. The circuit was designed to incorporate all the required electronic components within a 2.5” x 2” x 0.5” SL part. Electrical interconnects between electronic components were deposited on the SL part with a DW system using silver conductive ink lines. Several inks were deposited, cured, and tested on a variety of SL resin substrates, and the E 1660 ink (Ercon Inc, Wareham, MA) was selected due to its measured lowest average resistivity on the SL substrates. The finished circuit was compared with Printed Circuit Board (PCB) technology for functionality. The electronic components used here include a low voltage battery, LM 555 timer chip, resistors, a thermistor, capacitors, and Light Emitting Diodes (LEDs). This circuit was selected because it (1) represented a simple circuit combining many typically used electronic components and thus provided a useful demonstration for integrated electronic systems manufacturing applicable to a wide variety of devices, and (2) provided an indication of the parasitic resistances and capacitances introduced by the fabrication process due to its sensitivity to manufacturing variation. The hybrid technology can help achieve significant size reductions, enable systems integration in atypical forms, a natural resistance to reverse engineering and possibly increase maximum operating temperatures of electronic circuits as compared to the traditional PCB process. This research demonstrates the ability of the hybrid SL/DW technology for fabricating combined electronic systems for unique electronics applications in which arbitrary form is a requirement and traditional PCB technology cannot be used.Mechanical Engineerin

MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips

This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Stability, Causality, and Passivity in Electrical Interconnect Models

Modern packaging design requires extensive signal integrity simulations in order to assess the electrical performance of the system. The feasibility of such simulations is granted only when accurate and efficient models are available for all system parts and components having a significant influence on the signals. Unfortunately, model derivation is still a challenging task, despite the extensive research that has been devoted to this topic. In fact, it is a common experience that modeling or simulation tasks sometimes fail, often without a clear understanding of the main reason. This paper presents the fundamental properties of causality, stability, and passivity that electrical interconnect models must satisfy in order to be physically consistent. All basic definitions are reviewed in time domain, Laplace domain, and frequency domain, and all significant interrelations between these properties are outlined. This background material is used to interpret several common situations where either model derivation or model use in a computer-aided design environment fails dramatically.We show that the root cause for these difficulties can always be traced back to the lack of stability, causality, or passivity in the data providing the structure characterization and/or in the model itsel

Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)