Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

On-Chip Optical Interconnection Networks for Multi/Manycore Architectures

The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms

Architecture for Survivable System Processing (ASSP)

The Architecture for Survivable System Processing (ASSP) Program is a multi-phase effort to implement Department of Defense (DOD) and commercially developed high-tech hardware, software, and architectures for reliable space avionics and ground based systems. System configuration options provide processing capabilities to address Time Dependent Processing (TDP), Object Dependent Processing (ODP), and Mission Dependent Processing (MDP) requirements through Open System Architecture (OSA) alternatives that allow for the enhancement, incorporation, and capitalization of a broad range of development assets. High technology developments in hardware, software, and networking models, address technology challenges of long processor life times, fault tolerance, reliability, throughput, memories, radiation hardening, size, weight, power (SWAP) and security. Hardware and software design, development, and implementation focus on the interconnectivity/interoperability of an open system architecture and is being developed to apply new technology into practical OSA components. To insure for widely acceptable architecture capable of interfacing with various commercial and military components, this program provides for regular interactions with standardization working groups (e.g.) the International Standards Organization (ISO), American National Standards Institute (ANSI), Society of Automotive Engineers (SAE), and Institute of Electrical and Electronic Engineers (IEEE). Selection of a viable open architecture is based on the widely accepted standards that implement the ISO/OSI Reference Model

Time-cost effective factor of a Midimew connected Mesh network

Hierarchical Interconnection Network (HIN) is indispensable for the practical implementation of future generation massively parallel computer systems which consists of hundred thousands nodes or even millions of nodes. Because it yields good performance with low cost due to reduction of communication links and by exploring the locality in the communication & traffic patterns. A Midimew connected Mesh Network (MMN) is an HIN comprised of numerous basic modules, where the basic modules are 2D-mesh networks and they are hierarchically interconnected using midimew network to construct the higher level networks. In this paper, we present the architecture of a MMN and evaluate the time-cost effective factor of MMN, TESH, mesh, and torus networks. It is found that the proposed MMN yields slightly high time-cost effectiveness factor with small diameter and average distance as compared to other networks. Overall, performance with respect to time-cost effectiveness factor with small diameter and average distance suggests that the proposed MMN will be a indispensable choice for the next generation massively parallel computer systems

Design and implementation of an electro-optical backplane with pluggable in-plane connectors

The design, implementation and characterisation of an electro-optical backplane and an active pluggable in-plane optical connector technology is presented. The connection architecture adopted allows line cards to be mated to and unmated from a passive electro-optical backplane with embedded polymeric waveguides. The active connectors incorporate a photonics interface operating at 850 nm and a mechanism to passively align the interface to the optical waveguides embedded in the backplane. A demonstration platform has been constructed to assess the viability of embedded electro-optical backplane technology in dense data storage systems. The demonstration platform includes four switch cards, which connect both optically and electronically to the electro-optical backplane in a chassis. These switch cards are controlled by a single board computer across a Compact PCI bus on the backplane. The electrooptical backplane is comprised of copper layers for power and low speed bus communication and one polymeric optical layer, wherein waveguides have been patterned by a direct laser writing scheme. The optical waveguide design includes densely arrayed multimode waveguides with a centre to centre pitch of 250μm between adjacent channels, multiple cascaded waveguide bends, non-orthogonal crossovers and in-plane connector interfaces. In addition, a novel passive alignment method has been employed to simplify high precision assembly of the optical receptacles on the backplane. The in-plane connector interface is based on a two lens free space coupling solution, which reduces susceptibility to contamination. Successful transfer of 10.3 Gb/s data along multiple waveguides in the electro-optical backplane has been demonstrated and characterised

Optical interconnections embedded in flexible substrates

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