On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.This work has been partially funded by the Spanish Government project TEC-2007-68072 and the CSIC project 200850I213.Peer reviewe

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.Gobierno de España TEC-2007-68072Consejo Superior de Investigaciones Científicas 200850I21

Wireless sensor platform for harsh environments

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna

Circuit modeling of a MEMS varactor including dielectric charging dynamics

Electrical models for MEMS varactors including the effect of dielectric charging dynamics are not available in commercial circuit simulators. In this paper a circuit model using lumped ideal elements available in the Cadence libraries and a basic Verilog-A model, has been implemented. The model has been used to simulate the dielectric charging in function of time and its effects over the MEMS capacitance value.Peer ReviewedPostprint (published version

Multichannel biomedical telemetry system using delta modulation

Telemetering of biomedical data from unrestrained subjects requires a system to be compact, reliable and efficient. A survey of the existing multi-channel biomedical telemetry showed that most of the systems employ analogue or uncoded (digital) techniques of encoding biomedical signals. These techniques are less reliable, employ wider bandwidth and are difficult to implement compared to the coded (digital) techniques of modulation. A theoretical study of the coded techniques of modulation for encoding biomedical signals showed-that pulse code modulation, though more efficient, calls for extensive circuitry and makes it expensive and difficult to implement. Delta modulation and delta sigma modulation were found to be simpler, easier to Implement and efficient. [Continues.

A miniaturized digital telemetry system for physiological data transmission

A physiological date telemetry system, consisting basically of a portable unit and a ground base station was designed, built, and tested. The portable unit to be worn by the subject is composed of a single crystal controlled transmitter with AM transmission of digital data and narrowband FM transmission of voice; a crystal controlled FM receiver; thirteen input channels follwed by a PCM encoder (three of these channels are designed for ECG data); a calibration unit; and a transponder control system. The ground base station consists of a standard telemetry reciever, a decoder, and an FM transmitter for transmission of voice and transponder signals to the portable unit. The ground base station has complete control of power to all subsystems in the portable unit. The phase-locked loop circuit which is used to decode the data, remains in operation even when the signal from the portable unit is interrupted

Programmable CMOS Analog-to-Digital Converter Design and Testability

In this work, a programmable second order oversampling CMOS delta-sigma analog-to-digital converter (ADC) design in 0.5µm n-well CMOS processes is presented for integration in sensor nodes for wireless sensor networks. The digital cascaded integrator comb (CIC) decimation filter is designed to operate at three different oversampling ratios of 16, 32 and 64 to give three different resolutions of 9, 12 and 14 bits, respectively which impact the power consumption of the sensor nodes. Since the major part of power consumed in the CIC decimator is by the integrators, an alternate design is introduced by inserting coder circuits and reusing the same integrators for different resolutions and oversampling ratios to reduce power consumption. The measured peak signal-to-noise ratio (SNR) for the designed second order delta-sigma modulator is 75.6dB at an oversampling ratio of 64, 62.3dB at an oversampling ratio of 32 and 45.3dB at an oversampling ratio of 16. The implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ΔIDDQ testing of CMOS data converters is also presented. The BICS uses frequency as the output for fault detection in CUT. A fault is detected when the output frequency deviates more than ±10% from the reference frequency. The output frequencies of the BICS for various model parameters are simulated to check for the effect of process variation on the frequency deviation. A design for on-chip testability of CMOS ADC by linear ramp histogram technique using synchronous counter as register in code detection unit (CDU) is also presented. A brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design are described. Registers in this design are replaced by 6T-SRAM cells and a hardware optimized on-chip testability of CMOS ADC by linear ramp histogram technique using 6T-SRAM as register in CDU is presented. The on-chip linear ramp histogram technique can be seamlessly combined with ΔIDDQ technique for improved testability, increased fault coverage and reliable operation