Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret

Du fait de l'augmentation de la demande de produits pour les applications grand public, industrielles et automobiles, des mémoires embarquées fiables et à faible coût de fabrication sont de plus en plus demandées. Dans ce contexte, les mémoires split-gate à piégeage discret sont proposées pour des microcontrôleurs. Elles combinent l'avantage d'une couche de stockage discrète et de la con guration split-gate. Durant ce travail de recherche, des mémoires split-gate à couche de piégeage discret ayant des longueurs de grille de 20nm sont présentées pour la première fois. Celles-ci on été réalisées avec des nanocristaux de silicium (Si-nc), du nitrure de silicium (SiN) ou un hybride Si-nc/SiN avec diélectrique de control de type SiO2 ou AlO et sont comparées en termes de performances lors des procédures d'eff acement et de rétention. Ensuite, la miniaturisation des mémoires split-gate à piégeage de charge est étudié, en particulier au travers de l'impact de la réduction de la longueur de grille sur la fenêtre de mémorisation, la rétention et la consommation. Le rôle des défauts dans le diélectrique de contrôle (alumine) utilisé dans les mémoires de type TANOS a été étudié. Des travaux ont été menés pour déterminer l'origine des pièges dans ce matériau, par le biais de la simulation atomistique ainsi que d'analyses physico-chimiques précises. Nous avons montré que la concentration de pièges dans AlO pouvait être réduite par ajustement des conditions de procédé de fabrication, débouchant ainsi sur l'amélioration de la rétention dans les mémoires à piégeage de charge. Ce résultat est convenable pour les applications de type embarquéDue to the increasing demand for consumer, industrial and automotive products, highly reliable, and low integration cost embedded memories are more and more required. In this context, split-gate charge trap memories were proposed for microcontroller products, combining the advantage of a discrete storage layer and of the split-gate con guration. In this thesis, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-nc), or silicon nitride (SiN) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or AlO control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. We thus studied the role of defects on alumina control dielectric employed in TANOS-like memory. We used atomistic simulation, consolidated by a detailed alumina physico-chemical material analysis, to investigate the origin of traps in alumina. We showed that the trap concentration in AlO can be decreased by adjusting the process conditions leading to improved retention behaviour in charge trap memory, suitable for embedded applications.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen

Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung Abstract 1 Einleitung 2 Grundlagen aktiver Halbleiterelemente 2.1 Die MOS-Struktur 2.2 Der MOS-Feldeffekt-Transistor 2.3 Nichtflüchtige Festkörperspeicher 2.4 Speicherarchitekturen 2.5 Charakterisierungsmethoden von Halbleiter-Speicherelementen 3 Defektbasierte Ladungsspeicherung in dielektrischen Schichten 3.1 Physikalische Grundlagen von Haftstellen 3.2 Betrachtung der vertikalen Ladungsverteilung mit Hilfe von Simulationen 3.3 Ableitung der vertikalen Ladungsverteilung aus Messungen 4 Elektrisches Verhalten einer haftstellen-basierten Speicherzelle 4.1 Auswirkung von inhomogen verteilter Ladung in der Speicherschicht 4.2 Auswirkungen von Al2O3-Topoxid auf das Zellverhalten 4.3 Auswirkung des Steuerelektrodenmaterials auf das Zellverhalten 4.4 Einfluss von Kanal- und Source/Drain-Dotierung 5 Integration in eine stark skalierte NAND Architektur 5.1 Auswirkung struktureller Effekte auf die Speicherzelle 5.2 Störmechanismen beim Betrieb von stark skalierten NAND-Speichern 6 Zusammenfassung und Ausblick 6.1 Zusammenfassung 6.2 Ausblick Danksagung Lebenslauf Symbol- und Abkürzungsverzeichnis Literaturverzeichni

Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen

Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung Abstract 1 Einleitung 2 Grundlagen aktiver Halbleiterelemente 2.1 Die MOS-Struktur 2.2 Der MOS-Feldeffekt-Transistor 2.3 Nichtflüchtige Festkörperspeicher 2.4 Speicherarchitekturen 2.5 Charakterisierungsmethoden von Halbleiter-Speicherelementen 3 Defektbasierte Ladungsspeicherung in dielektrischen Schichten 3.1 Physikalische Grundlagen von Haftstellen 3.2 Betrachtung der vertikalen Ladungsverteilung mit Hilfe von Simulationen 3.3 Ableitung der vertikalen Ladungsverteilung aus Messungen 4 Elektrisches Verhalten einer haftstellen-basierten Speicherzelle 4.1 Auswirkung von inhomogen verteilter Ladung in der Speicherschicht 4.2 Auswirkungen von Al2O3-Topoxid auf das Zellverhalten 4.3 Auswirkung des Steuerelektrodenmaterials auf das Zellverhalten 4.4 Einfluss von Kanal- und Source/Drain-Dotierung 5 Integration in eine stark skalierte NAND Architektur 5.1 Auswirkung struktureller Effekte auf die Speicherzelle 5.2 Störmechanismen beim Betrieb von stark skalierten NAND-Speichern 6 Zusammenfassung und Ausblick 6.1 Zusammenfassung 6.2 Ausblick Danksagung Lebenslauf Symbol- und Abkürzungsverzeichnis Literaturverzeichni

Silica and Silicon Based Nanostructures

Silica and silicon-based nanostructures are now well-understood materials for which the technologies are mature. The most obvious applications, such as electronic devices, have been widely explored over the last two decades. The aim of this Special Issue is to bring together the state of the art in the field and to enable the emergence of new ideas and concepts for silicon and silica-based nanostructures

Towards end-to-end security in internet of things based healthcare

Healthcare IoT systems are distinguished in that they are designed to serve human beings, which primarily raises the requirements of security, privacy, and reliability. Such systems have to provide real-time notifications and responses concerning the status of patients. Physicians, patients, and other caregivers demand a reliable system in which the results are accurate and timely, and the service is reliable and secure. To guarantee these requirements, the smart components in the system require a secure and efficient end-to-end communication method between the end-points (e.g., patients, caregivers, and medical sensors) of a healthcare IoT system. The main challenge faced by the existing security solutions is a lack of secure end-to-end communication. This thesis addresses this challenge by presenting a novel end-to-end security solution enabling end-points to securely and efficiently communicate with each other. The proposed solution meets the security requirements of a wide range of healthcare IoT systems while minimizing the overall hardware overhead of end-to-end communication. End-to-end communication is enabled by the holistic integration of the following contributions. The first contribution is the implementation of two architectures for remote monitoring of bio-signals. The first architecture is based on a low power IEEE 802.15.4 protocol known as ZigBee. It consists of a set of sensor nodes to read data from various medical sensors, process the data, and send them wirelessly over ZigBee to a server node. The second architecture implements on an IP-based wireless sensor network, using IEEE 802.11 Wireless Local Area Network (WLAN). The system consists of a IEEE 802.11 based sensor module to access bio-signals from patients and send them over to a remote server. In both architectures, the server node collects the health data from several client nodes and updates a remote database. The remote webserver accesses the database and updates the webpage in real-time, which can be accessed remotely. The second contribution is a novel secure mutual authentication scheme for Radio Frequency Identification (RFID) implant systems. The proposed scheme relies on the elliptic curve cryptography and the D-Quark lightweight hash design. The scheme consists of three main phases: (1) reader authentication and verification, (2) tag identification, and (3) tag verification. We show that among the existing public-key crypto-systems, elliptic curve is the optimal choice due to its small key size as well as its efficiency in computations. The D-Quark lightweight hash design has been tailored for resource-constrained devices. The third contribution is proposing a low-latency and secure cryptographic keys generation approach based on Electrocardiogram (ECG) features. This is performed by taking advantage of the uniqueness and randomness properties of ECG's main features comprising of PR, RR, PP, QT, and ST intervals. This approach achieves low latency due to its reliance on reference-free ECG's main features that can be acquired in a short time. The approach is called Several ECG Features (SEF)-based cryptographic key generation. The fourth contribution is devising a novel secure and efficient end-to-end security scheme for mobility enabled healthcare IoT. The proposed scheme consists of: (1) a secure and efficient end-user authentication and authorization architecture based on the certificate based Datagram Transport Layer Security (DTLS) handshake protocol, (2) a secure end-to-end communication method based on DTLS session resumption, and (3) support for robust mobility based on interconnected smart gateways in the fog layer. Finally, the fifth and the last contribution is the analysis of the performance of the state-of-the-art end-to-end security solutions in healthcare IoT systems including our end-to-end security solution. In this regard, we first identify and present the essential requirements of robust security solutions for healthcare IoT systems. We then analyze the performance of the state-of-the-art end-to-end security solutions (including our scheme) by developing a prototype healthcare IoT system

A Solder-Defined Computer Architecture for Backdoor and Malware Resistance

This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection. The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic. The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed

Design and Application of Wireless Body Sensors

Hörmann T. Design and Application of Wireless Body Sensors. Bielefeld: Universität Bielefeld; 2019

Polymer Films for Photovoltaic Applications

Reprints of Polymers Special Issue entitled "Polymer films for photovoltaic applications", which covers all fields related to polymer films for photovoltaic applications, but special attention will be given to the following aspects:- The synthesis and suitable modification of polymer structure, to obtain polymer thin films for PV devices;- The influence of film deposition (thermal vacuum evaporation (TVE), chemical vapor deposition (CVD), spin coating, spray, etc.) on the properties of polymer films;- The thermo-optical properties of polymer thin films and blends of polymer films, as potential parts of PV systems;- The influence of doping or protonation of polymer thin films and blend polymer films on their properties;- Polymer thin films as active layers in PV solar cells—correlation of chemical structure and PV properties;- BHJ solar cells with polymer blends films—the choice of blend film composition to obtain the best PV parameters

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 12)

For abstract, see N78-27983

NASA patent abstracts bibliography: A continuing bibliography. Section 2: Indexes (supplement 10)

Abstracts for 3089 patents and applications for patent entered in the NASA scientific and information system for the period covering May 1969 through December 1976 are indexed by subject, inventor, source, NASA case or U.S. patent number, and accession number in the NASA system