GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

Die gedruckte Elektronik ist ein im Vergleich zur konventionellen Siliziumtechnologie junges Forschungsgebiet. Die Idee hinter der gedruckten Elektronik ist es elektronische Bauteile wie Widerstände, Kapazitäten, Solarzellen, Dioden und Transistoren mit gängigen Druckmethoden herzustellen. Dabei ist es möglich die elektronischen Bauteile auf unbiegsamen Substrate, wie Glas oder Silizium, als auch auf biegsamen Substrate, wie Papier und Folie, zu drucken. Aufgrund des Druckprozesses, sind die Herstellungskosten gering, da drucken ein additiver Prozess ist und somit teure Masken obsolet sind. In einem Feldeffekttransistor, wird der Halbleiter zwischen zwei Elektroden (Drain- und Source) gedruckt. Die Drain- und Source-Elektroden werden dabei durch einen Vakuum- oder Druckprozess abgeschieden und strukturiert. Der halbleitende Kanal wird durch einen Dielektrikum von der Gate-Elektrode isoliert. Auch für das Dielektrikum und die Gate-Elektrode sind ein Vakuum- oder Druckprozess denkbar. Standardmäßig finden organische Materialien Einsatz in der gedruckten Elektronik. Leider weisen organische Halbleiter, in einem Feldeffekttransistor, nur eine geringe Ladungsträgerbeweglichkeit ($\leq 1$ cm$^2$(Vs)$^{-1}$) auf. Die niedrige Ladungsträgerbeweglichkeit führt zu einer geringen Ladungsträgerdichte im Halbleiter und als Resultat zu geringen Stromdichten. Auch sind größtenteils nur p-leitende Halbleiter für den Einsatz in Schaltungen vorhanden, weswegen die meisten Schaltungen nur p-leitende Feldeffekttransistoren besitzen. Ein weiterer Nachteil der organischen Elektronik ist, dass die eingesetzten Dielektrika mit dem Halbleiter eine mangelhafte Grenzfläche bildet. Deshalb sind Versorgungsspannungen in Bereich von 5 V keine Seltenheit. Eine interessante Alternative zu organischen Halbleitern sind Materialien die der Kategorie der Oxide zugeordnet sind. Zum Beispiel in Indiumoxid (In$_{2}$O$_{3}$) ist eine Ladungsträerbeweglichkeit um die 100 cm$^2$(Vs)$^{-1}$ messbar. Leider sind durch Oxide realisierte p-leitende Feldeffekttransistoren sehr selten, weshalb die meisten Schaltungen auf n-leitenden Feldeffekttransistoren basieren. Ein weiterer Nachteil von Metalloxidhalbleitern is das hohe Glühtemperaturen (\sim 400 \, ^\circC) benötigt werden um die richtige Kristallstruktur zu erzielen. Durch den Einsatz eines Elektrolyten, anstatt eines Dielektrikum, werden die benötigten hohen Versorgungsspannungen auf 1 V reduziert. Der Grund für die Reduzierung der Versorgungsspannung liegt in der hohen Kapazität ($\sim 5 \, \mu$F(cm)$^{-1}$), die sich zwischen der Gate-Elektrode und dem Kanal ausbildet. Die optimale Grenzfläche zwischen der Gate-Elektrode und dem Elektrolyten sowie als auch zwischen dem Elektrolyten und dem Kanal, wo sich eine Helmholtz-Doppelschicht ausbildet, ist der Grund für die hohe Kapazität. In dieser Arbeit, werden die Vorteile der hohen Ladungsträgerbeweglichkeit, resultierend von einem Indiumoxid-Kanal, und der niedrigen Versorgungsspannungen, durch den Einsatz eines Elektrolyten als Isolator, in einem gedruckten Transistor kombiniert. Daher ist das Ziel zunächst Transistoren basierend auf einem Elektrolyten und Indiumoxid-Kanal zu charakterisieren und zu modellieren. Auch werden Möglichkeiten zum Schaltungsentwurf mit der hier vorgestellten Transistortechnologie ausgearbeitet. Der Schaltungsentwurf wird anhand mikroelektronischen Zellen und Ringoszillator-Strukturen verifiziert. Wichtig für den Schaltungsentwurf sind Modelle die fähig sind die elektrischen Eigenschaften eines Transistors abzubilden. Dabei muss die simulierte Kurve Stetigkeit und Kontinuität aufweisen um Konvergenzprobleme während der Simulation zu verhindern. Zur Modellierung der elektrischen Eigenschaften und Ströme der Transistoren wird ein Modell basierend auf den Curtice-Modell entwickelt. Der Bereich über der Schwellwertspannung wird daher durch das Curtice-Modell abgebildet und der Bereich unter der Schwellspannung durch ein aus Siliziumtransistoren bekanntes Standard-Modell beschrieben. Kontinuität und Stetigkeit wird durch eine Interpolation zwischen den beiden Transistormodellen gewährleistet. Ein Verglich zwischen gemessenen und simulierten Daten zeigt das das Modell die hier vorgestellte Transistortechnologie sehr gut abbilden kann. Das entwickelte Transistormodel wird zur unterstützung des Schaltungsentwurf in einem Prozesskit (PDK) integriert. Dadurch ist das Verhalten einer Schaltung durch Simulation vorhersehbar. In der Simulation können auch der Einfluss der Umwelt, z.B. Luftfeuchtigkeit, auf die Transistoren analysiert werden. In der digitalen Schaltungstechnik wird ein p-leitender Feldeffekttransistor verwendet um ein Eingangssignal hochzusetzen, während um ein Signal runterzusetzen, ein n-leitender Feldeffekttransistor von Vorteil ist. Da p-leitende Oxide selten und unzuverlässig sind, wird der p-leitende Feldeffekttransistor durch einen Widerstand (Transistor-Widerstand-Logik (TRL)) oder einen n-leitenden Feldeffekttransistor (Transistor-Transistor-Logik (TTL)) ersetzt. Ein Inverter in TRL weist bei einer Versorgungsspannung von 1 V einen Verstärkungsfaktor von ungefähr -5 auf und eine Signalverzögerung von 0.9 ms. Die Oszillatorfrequenz im entsprechend Ringoszillator beträgt 296 Hz. Weitere Logikgatter (NAND, NOR und XOR) sind ebenfalls realisierbar mit TRL-Entwürfe. In TTL wird der p-leitende Feldeffekttransistor durch einen n-leitenden Verarmungstyps Feldeffekttransistor ersetzt. Die in der TTL entworfene Logikgatter verhalten sich identisch zu den TTR-Zellen aber die Frequenz vom Ringoszillator steigt bis in den unteren kHz-Bereich an. In TTL ist es ebenfalls möglich die Verlustleistung um einen Faktor von 6 zu reduzieren

Enhanced Logic Performance with Semiconducting Bilayer Graphene Channels

Realization of logic circuits in graphene with an energy gap (EG) remains one of the main challenges for graphene electronics. We found that large transport EGs (>100 meV) can be fulfilled in dual-gated bilayer graphene underneath a simple alumina passivation top gate stack, which directly contacts the graphene channels without an inserted buffer layer. With the presence of EGs, the electrical properties of the graphene transistors are significantly enhanced, as manifested by enhanced on/off current ratio, subthreshold slope and current saturation. For the first time, complementary-like semiconducting logic graphene inverters are demonstrated that show a large improvement over their metallic counterparts. This result may open the way for logic applications of gap-engineered graphene.Comment: Accepted by ACS Nan

페로브스카이트 산화물 BaSnO3 기반 시스템에서 2차원 전자 가스의 수송 특성

학위논문(박사) -- 서울대학교대학원 : 자연과학대학 물리·천문학부(물리학전공), 2023. 8. 차국린.BaSnO3 (BSO), also known as barium stannate, is a promising material with several excellent properties that have been reported so far. The superior properties of BSO compared to other perovskite oxides include: First, BSO can be easily doped with n-type dopants (especially, La dopant) and has high carrier density (n3D ~ 1020 cm-3) and high electron mobility (μ ~ 320 cm2·V-1·s-1 in single crystals and μ ~ 70 cm2·V-1·s-1 in thin films), which is the highest among other perovskite oxides at room temperature. This property is essential for achieving efficient charge transport in electronic devices, leading to improved device performance. Second, BSO possesses excellent transparency in the visible spectrum, allowing light to pass through without significant absorption or scattering. This property makes it suitable for optoelectronic devices like transparent displays, solar cells, and sensors. Third, BSO demonstrates good thermal stability, retaining its electrical and optical properties even at elevated temperatures. This stability is crucial for applications involving high-temperature operations, such as power electronics and solid oxide fuel cells. Forth, BSO demonstrates excellent chemical stability, showing resistance to degradation in various environments. This stability is advantageous for long-term device reliability and performance, particularly in harsh conditions or corrosive atmospheres. These excellent properties of BSO make it an intriguing material for a wide range of applications, including transparent field-effect transistors, energy harvesting, optoelectronics, and high-power devices. In this dissertation, my research is mainly focused on heterostructures between BSO and other perovskite oxides, especially LaInO3/BaSnO3 and LaScO3/BaSnO3 heterostructures, in which 2-dimensional electron gas (2DEG) was formed at each interface. With the introduction of interface polarization model based on the calculation of the self-consistent Poisson-Schrödinger simulations and the confirmation of structural modifications of the heterostructures verified with high-resolution transmission electron microscope, the analysis of 2DEG at the LaInO3/BaSnO3 interface was reaffirmed. And, previously unreported 2DEG generated at the LaScO3/BsSnO3 interface was confirmed through electrical and structural characteristics analyses, comparing the results with the LaInO3/BaSnO3 interface. The interface polarization model was applied to the LaScO3/BaSnO3 system, in which the polarization exists only over 4 pseudocubic unit cells in LaScO3 from the interface and vanishes afterward like the LaInO3/BaSnO3 interface. Based on the calculations of the self-consistent Poisson-Schrödinger equations, the LaScO3 thickness dependence of n2D of the LaScO3/BaSnO3 heterointerface is consistent with this model, and furthermore, a single subband in the quantum well is predicted. Finally, field-effect transistors composed solely of perovskite oxides with high field-effect mobility close to 100 cm2·V-1·s-1 at room temperature using conductive 2DEG interface and LaScO3 as the gate dielectric was demonstrated. Next, the possibilities of forming different types of 2-dimensional systems based on BSO are theoretically calculated using self-consistent Poisson-Schrödinger simulations. These include 2-dimensional hole gas (2DHG) generated at the LaScO3/BaSnO3 interface and 2-dimensional electron gas (2DEG) generated at the SrHfO3/BaSnO3 interfaces. As a result of running the simulations by varying adjustments of related parameters such as energy gap, conduction band offset to BSO, deep donor level, deep donor density, dielectric constant, effective mass, and polarization, 2-dimensional charge carriers could be formed at the interfaces of these new heterostructures. The theoretical calculations by the simulations are expected to be the basis for subsequent experiments in the future. LaInO3/BaSnO3 heterostructures has recently been studied as a promising platform for realizing 2DEG with excellent transport characteristics, including field-effect devices at room temperature, but its low-temperature behavior is still not well understood. So, detailed investigations of the low-temperature properties of 2DEG at the LaInO3/BaSnO3 interface were performed. Negative magnetoresistance measured in perpendicular and parallel magnetic fields and no increase in electron mobility at low-temperature from Hall measurement suggest that this system is under weak localization regimes due to the high density of disorders including defects or threading dislocations in the films. After that, fabrication of electric-double-layer transistor using ionic-liquid and application of liquid gating to BSO-based 2-dimensional systems are performed to improve transport properties by modulating the carriers at low-temperature. By using ionic-liquid gating, carriers were significantly modulated to more than 1 order, indicating that the feasibility of reversible liquid gating for carrier modulation in BSO-based 2-dimensional systems. Finally, several attempts to improve the electrical properties of BSO-based systems have been introduced, and preliminarily tested using 1% La-doped BSO (BLSO). First, the film was grown using new, previously unreported LaInO3 substrates with orthorhombic structure whose lattice constant is matched with the BLSO film. Second, a new previously unreported Sr1-xBaxHfO3 buffer layer whose lattice constant is matched with the BSO buffer layer was used. Last, it was checked whether the electrical properties of the BLSO film are effectively improved through adjustment of target-to-substrate spacing or subsequent high-temperature heat treatment. Then, the characteristics of previously reported BLSO films and those of BLSO films including the above trials were compared and analyzed.바륨 주석 산화물로도 알려진 BaSnO3(BSO)는 지금까지 보고된 몇 가지 우수한 특성을 가진 유망한 물질이다. 다른 페로브스카이트 산화물에 비해 BSO가 갖는 우수한 특성은 다음과 같다: 첫째, BSO는 n형 도펀트(특히, La dopant)로 쉽게 도핑될 수 있으며, 높은 캐리어 밀도(n3D ~1020 cm-3)와 높은 전자 이동성(단결정의 경우 μ ~ 320 cm2·V-1·s-1 및 박막의 경우 μ ~ 70 cm2·V-1·s-1)을 가지고 있어 상온에서 다른 페로브스카이트 산화물 중 가장 높다. 이 특성은 전자 장치에서 효율적인 전하 수송을 달성하여 장치 성능을 향상시키는 데 필수적이다. 둘째, BSO는 가시 스펙트럼에서 우수한 투명도를 가지고 있어 빛이 상당한 흡수나 산란 없이 통과할 수 있다. 이러한 특성으로 인해 투명 디스플레이, 태양 전지, 그리고 센서와 같은 광전자 장치에 적합하다. 셋째, BSO는 높은 온도에서도 전기적, 광학적 특성을 유지하면서 우수한 열 안정성을 보여준다. 이러한 안정성은 전력 전자 장치 및 고체 산화물 연료 전지와 같은 고온 작동과 관련된 애플리케이션에 매우 중요하다. 넷째, BSO는 우수한 화학적 안정성을 보여주며 다양한 환경에서 열화에 대한 내성을 보여준다. 이러한 안정성은 특히 가혹한 조건이나 부식성 환경에서 장기적인 장치 신뢰성과 성능에 유리하다. BSO의 이러한 우수한 특성은 투명 전계 효과 트랜지스터, 에너지 하베스팅, 광전자 및 고출력 장치를 포함한 광범위한 응용 분야에 흥미로운 재료가 된다. 본 논문에서는 주로 BSO와 다른 페로브스카이트 산화물 사이의 헤테로 구조, 특히 LaInO3/BaSnO3와 LaScO3/BaSnO3 헤테로 구조에 대한 연구를 진행하고 있으며, 각 계면에 2차원 전자 가스(2DEG)가 형성되어 있다. 자체 일관성 있는 포아송-슈뢰딩거 시뮬레이션의 계산과 고해상도 투과 전자 현미경으로 검증된 이종 구조의 구조적 변조의 확인에 기반한 계면 분극 모델의 도입으로 LaInO3/BaSnO3 계면에서 2DEG의 분석이 재확인되었다. 그리고, 전기적, 구조적 특성 분석을 통해 LaScO3/BaSnO3 계면에서 기존에 보고되지 않은 2DEG가 발생한 것을 확인하고, 그 결과를 LaInO3/BaSnO3 계면과 비교하였다. 계면 분극 모델은 LaScO3/BaSnO3 시스템에 적용되었는데, 분극은 계면에서 LaScO3의 4 개의 유사 입방 단위 셀에만 존재하고 이후에는 LaInO3/BaSnO3 계면처럼 소멸된다. 자체 일관성 있는 포아송-슈뢰딩거 방정식의 계산에 따르면, LaScO3/BaSnO3 헤테로 계면에서 생성되는 n2D의 LaScO3 두께 의존성은 이 모델과 일치하며, 나아가 양자 우물의 단일 서브 밴드를 예측한다. 마지막으로 전도성 2DEG 채널과 LaScO3를 게이트 유전체로 사용하여 상온에서 100 cm2·V-1·s-1에 가까운 높은 전계 효과 이동도를 갖는 페로브스카이트 산화물로만 구성된 전계 효과 트랜지스터가 시연되었다. 다음으로, BSO를 기반으로 한 다른 유형의 2차원 시스템을 형성할 수 있는 가능성이 자체 일관성 있는 포아송-슈뢰딩거 시뮬레이션을 사용하여 이론적으로 계산되었다. 여기에는 LaScO3/BaSnO3 계면에서 생성되는 2차원 홀 가스(2DHG)와 SrHfO3/BaSnO3 계면에서 생성되는 2차원 전자 가스(2DEG)가 포함된다. 에너지 갭, BSO에 대한 전도대 오프셋, 깊은 도너 수준, 깊은 도너 밀도, 유전 상수, 유효 질량 및 분극화와 같은 관련 매개변수를 다양하게 조정하여 시뮬레이션을 실행한 결과, 2차원 전하 캐리어가 이러한 새로운 헤테로 구조의 계면에 형성될 수 있었다. 시뮬레이션에 의한 이론적 계산은 향후 후속 실험의 기초가 될 것으로 기대된다. LaInO3/BaSnO3 이종 구조는 최근 상온에서 전계 효과 소자를 포함하여 우수한 수송 특성을 갖는 2DEG를 구현하기 위한 유망한 플랫폼으로 연구되고 있으나, 그 저온 거동은 여전히 잘 이해되지 않고 있다. 따라서, 본 논문에서는 LaInO3/BaSnO3 계면에서 형성되는 2DEG의 저온 특성에 대한 자세한 연구가 수행되었다. 수직 및 평행 자기장에서 측정된 음의 자기 저항과 홀 측정으로부터 저온에서 전자 이동성이 증가하지 않는다는 것은 이 시스템이 박막의 결함 및 스레딩 전위를 포함한 높은 밀도의 무질서 상태로 인해 약한 국소화 체제 하에 있음을 시사한다. 그 후, 이온성 액체를 이용한 전기 이중 층 트랜지스터의 제작 및 BSO계 2차원 시스템으로의 액체 게이팅을 수행하여 저온에서 캐리어를 변조하여 수송 특성을 향상시켰다. 이온-액체 게이팅을 사용함으로써 캐리어는 1차 이상으로 크게 변조되었으며, 이는 BSO 기반 2차원 시스템에서 캐리어 변조를 위한 가역적 액체 게이팅의 가능성을 나타낸다. 마지막으로, BSO 기반 시스템의 전기적 특성을 개선하기 위한 몇 가지 시도가 도입되었고, 1% La-doped BSO(BLSO)를 사용하여 사전 테스트되었다. 먼저, 박막은 격자 상수가 BLSO 박막과 일치하는 사방 정계 구조를 가진 이전에 보고되지 않은 새로운 LaInO3 기판을 사용하여 성장되었다. 둘째, 격자 상수가 BSO 버퍼 층과 일치하는 이전에 보고되지 않은 새로운 Sr1-xBaxHfO3 버퍼 층이 사용되었다. 마지막으로, BLSO 박막의 전기적 특성이 타겟-기판 간격 조정 혹은 후속 고온 열처리를 통해 효과적으로 개선되는지 확인하였다. 그런 다음, 기존에 보고된 BLSO 박막과 상기 시도를 포함하는 BLSO 박막의 특성을 비교 및 분석하였다.Abstract i List of Contents v List of Figures viii List of Tables xvi 1. Introduction 1 1.1. Perovskite oxide semiconductors 1 1.2. BaSnO3 properties 1 1.2.1. High mobility 2 1.2.2. Low diffusion coefficient 3 1.2.3. 2-dimensional electron gas 4 1.2.4. Field-effect transistor 5 2. 2-dimensional systems formed with BaSnO3 – I. Basic 8 2.1. Introduction 8 2.2. 2-dimensional electron gas at the LaInO3/BaSnO3 interface 10 2.2.1. Analysis using Poisson-Schrödinger simulations 12 2.2.2. Origin of polarization at the interface 18 2.3. 2-dimensional electron gas at the LaScO3/BaSnO3 interface 20 2.3.1. Dielectric characteristics of LaScO3 film 23 2.3.2. Electrical characteristics of heterostructures 26 2.3.3. Structural analysis of heterostructures 33 2.3.4. Field-effect transistor using 2DEG channel 37 2.4. Conclusion 40 3. 2-dimensional systems formed with BaSnO3 – II. Expansion 41 3.1. Introduction 41 3.2. Termination layer control to enhance the 2DEG state at the interface 42 3.3. Possibilities of new 2-dimensional systems based on BaSnO3 50 3.3.1. 2-dimensional hole gas at the LaScO3/BaSnO3 interface 51 3.3.2. 2-dimensional electron gas at the SrHfO3/BaSnO3 interface 55 3.4. Conclusion 59 4. Low-temperature characteristics of BaSnO3-based systems 61 4.1. Introduction 61 4.2. Low-temperature measurement and analysis of the LaInO3/BaSnO3 2DEG and δ-doped BaSnO3 62 4.2.1. Sample preparation 63 4.2.2. Temperature dependence of sheet resistance 67 4.2.3. Negative magnetoresistance 68 4.2.4. Hall measurement 74 4.3. Ionic-liquid gating for carrier modulation 75 4.3.1. Sample preparation for ionic-liquid gating 76 4.3.2. Temperature dependence of sheet resistance 78 4.3.3. Negative magnetoresistance 80 4.3.4. Hall measurement 83 4.4. Conclusion 86 5. Efforts to improve electrical properties of La-doped BaSnO3 88 5.1. Introduction 88 5.2. Change of substrate – LaInO3 substrate 91 5.2.1. LaInO3 substrate in (100) orientation 92 5.2.2. LaInO3 substrate in (110) orientation 94 5.3. Change of buffer layer – Sr1-xBaxHfO3 film 97 5.4. Change of target-to-substrate distance 102 5.5. Conclusion 107 6. Summary 108 Bibliography 110 List of publications 124 List of presentations 125 Abstract in Korean 126박

OFF-State Reliability of pGaN Power HEMTs

The concern for climate changes and the increase in the electricity demand turned the attention towards the production, sorting and use of electric energy through zero emission (CO2) and highly efficient solutions (e.g. for electric vehicle), respectively. As a consequence, the need for high performance, reliable and low cost power transistors adopted for power applications is increasing as well. Gallium nitride seems to be the most promising candidate for the next generation of devices for power electronics, thanks to its excellent properties and comparable cost with respect to Si counterpart. The main and most adopted GaN-based device is the high electron mobility transistor (HEMT). In particular, in the case of switching power applications, HEMTs repeatedly are switched between high current on-state and high voltage off-state operation. For both operation modes a good reliability must be guaranteed. This thesis is focused on the reliability issues related to the off-state operation. The results have been obtained during a six months research period at imec (Belgium) on 200V p-GaN gate AlGaN/GaN HEMTS. Different devices have been investigated, differing for gate-to-drain distance, field plates lengths, AlGaN and GaN layers properties. Time-dependent dielectric breakdown and hard breakdown tests have been performed in combination with TCAD simulations. It has been demonstrated that the gate-to-drain distance (LGD) impacts the breakdown voltage and the kind of failure mechanism. If LGD ≤3um the breakdown occurs through the GaN channel layer due to short channel effects. In this case, by reducing the thickness of the GaN channel layer such behaviour can be attenuated, eventually leading to longer time-to-failure. If LGD≥ 4um the breakdown occurs between the 2DEG and the source field plates, where the properties of the AlGaN barrier layer (i.e. thickness and Al concentration) and the field plates configuration play the main role on the time-to-failure

Multi-criteria optimization for energy-efficient multi-core systems-on-chip

The steady down-scaling of transistor dimensions has made possible the evolutionary progress leading to today’s high-performance multi-GHz microprocessors and core based System-on-Chip (SoC) that offer superior performance, dramatically reduced cost per function, and much-reduced physical size compared to their predecessors. On the negative side, this rapid scaling however also translates to high power densities, higher operating temperatures and reduced reliability making it imperative to address design issues that have cropped up in its wake. In particular, the aggressive physical miniaturization have increased CMOS fault sensitivity to the extent that many reliability constraints pose threat to the device normal operation and accelerate the onset of wearout-based failures. Among various wearout-based failure mechanisms, Negative biased temperature instability (NBTI) has been recognized as the most critical source of device aging. The urge of reliable, low-power circuits is driving the EDA community to develop new design techniques, circuit solutions, algorithms, and software, that can address these critical issues. Unfortunately, this challenge is complicated by the fact that power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on compact architectures, scaled supply voltages, and small devices. This dissertation focuses on methodologies to bridge this gap and establishes an important link between low-power solutions and aging effects. More specifically, we proposed new architectural solutions based on power management strategies to enable the design of low-power, aging aware cache memories. Cache memories are one of the most critical components for warranting reliable and timely operation. However, they are also more susceptible to aging effects. Due to symmetric structure of a memory cell, aging occurs regardless of the fact that a cell (or word) is accessed or not. Moreover, aging is a worst-case matric and line with worst-case access pattern determines the aging of the entire cache. In order to stop the aging of a memory cell, it must be put into a proper idle state when a cell (or word) is not accessed which require proper management of the idleness of each atomic unit of power management. We have proposed several reliability management techniques based on the idea of cache partitioning to alleviate NBTI-induced aging and obtain joint energy and lifetime benefits. We introduce graceful degradation mechanism which allows different cache blocks into which a cache is partitioned to age at different rates. This implies that various sub-blocks become unreliable at different times, and the cache keeps functioning with reduced efficiency. We extended the capabilities of this architecture by integrating the concept of reconfigurable caches to maintain the performance of the cache throughout its lifetime. By this strategy, whenever a block becomes unreliable, the remaining cache is reconfigured to work as a smaller size cache with only a marginal degradation of performance. Many mission-critical applications require guaranteed lifetime of their operations and therefore the hardware implementing their functionality. Such constraints are usually enforced by means of various reliability enhancing solutions mostly based on redundancy which are not energy-friendly. In our work, we have proposed a novel cache architecture in which a smart use of cache partitions for redundancy allows us to obtain cache that meet a desired lifetime target with minimal energy consumption

Design and develop a MOS magnetic memory Final report, 11 Mar. - 11 Sep. 1966

Interface problems between plated wire magnetic memory and MO

Characterization of Charge Trapping Phenomena in GaN-based HEMTs

This dissertation reports on charge-trapping phenomena and related parasitic effects in AlGaN/GaN high electron mobility transistors. By means of static and pulsed I-V measurements and deep-level transient spectroscopy, the main charge-trapping mechanisms affecting the dynamic performance of GaN-based HEMTs devoted to microwave and power switching applications have been comprehensively characterized, identifying the nature and the localization of the deep-levels responsible for the electrically active trap-states. A high-voltage measurement system capable for double-pulsed ID-VD, ID-VG and drain-current transient spectroscopy has been successfully designed and implemented. A characterization methodology, including the analysis of static I-V measurements, pulsed I-V measurements, and deep-level transient spectroscopy, has been developed to investigate the impact of voltage, current, and temperature on the parasitic effects of charge-trapping (threshold voltage instabilities, dynamic on-resistance increase, and transconductance reduction), and on trapping/detrapping kinetics. Experimental results gathered on transistor structures are supported by complementary capacitance deep-level transient spectroscopy (C-DLTS) performed on 2-terminal diode (FATFET) structures. Two main case-studies have been investigated. Schottky-gated AlGaN/GaN HEMTs grown on silicon carbide substrate employing iron and/or carbon doped buffers devoted to microwave applications, and MIS-gated double-heterostructure AlGaN/GaN/AlGaN HEMTs grown on silicon substrate devoted to power switching applications. The devices under test have been exposed to the complete set of current-voltage regimes experienced during the real life operations, including off-state, semi-on-state, and on-state. The main novel results are reported in the following: • Identification of a charge-trapping mechanism promoted by hot-electrons. This mechanism is critical in semi-on-state, with the combination of relatively high electric-field and relatively high drain-source current. • Identification of a positive temperature-dependent charge-trapping mechanism localized in the buffer-layer, potentially promoted by the vertical drain to substrate potential. This mechanism is critical in high drain-voltage off-state bias in high temperature operations. • Identification of deep-levels and charge-trapping related to the presence of doping compensation agents (iron and carbon) within the GaN buffer layer. • Identification of charge-trapping mechanism ascribed to the SiNX and/or Al2O3 insulating layers of MIS-gated HEMTs. This mechanism is promoted in the on-state with positive gate-voltage and positive gate leakage current. • Identification of a potential charge-trapping mechanism ascribed to reverse gate leakage current in Schottky-gate HEMTs exposed to high-voltage off-state. • The characterization of surface-traps in ungated and unpassivated devices by means of drain-current transient spectroscopy reveals a non-exponential and weakly thermally-activated detrapping behaviour. • Preliminary synthesis of a degradation mechanism characterized by the generation of defect-states, the worsening of parasitic charge-trapping effects, and the degradation of rf performance of AlGaN/GaN HEMTs devoted to microwave operations. The evidence of this degradation mechanism is appreciable only by means of rf or pulsed I-V measurements: no apparent degradation is found by means of DC analysis