Improve the Usability of Polar Codes: Code Construction, Performance Enhancement and Configurable Hardware

Error-correcting codes (ECC) have been widely used for forward error correction (FEC) in modern communication systems to dramatically reduce the signal-to-noise ratio (SNR) needed to achieve a given bit error rate (BER). Newly invented polar codes have attracted much interest because of their capacity-achieving potential, efficient encoder and decoder implementation, and flexible architecture design space.This dissertation is aimed at improving the usability of polar codes by providing a practical code design method, new approaches to improve the performance of polar code, and a configurable hardware design that adapts to various specifications. State-of-the-art polar codes are used to achieve extremely low error rates. In this work, high-performance FPGA is used in prototyping polar decoders to catch rare-case errors for error-correcting performance verification and error analysis. To discover the polarization characteristics and error patterns of polar codes, an FPGA emulation platform for belief-propagation (BP) decoding is built by a semi-automated construction flow. The FPGA-based emulation achieves significant speedup in large-scale experiments involving trillions of data frames. The platform is a key enabler of this work. The frozen set selection of polar codes, known as bit selection, is critical to the error-correcting performance of polar codes. A simulation-based in-order bit selection method is developed to evaluate the error rate of each bit using Monte Carlo simulations. The frozen set is selected based on the bit reliability ranking. The resulting code construction exhibits up to 1 dB coding gain with respect to the conventional bit selection. To further improve the coding gain of BP decoder for low-error-rate applications, the decoding error mechanisms are studied and analyzed, and the errors are classified based on their distinct signatures. Error detection is enabled by low-cost CRC concatenation, and post-processing algorithms targeting at each type of the error is designed to mitigate the vast majority of the decoding errors. The post-processor incurs only a small implementation overhead, but it provides more than an order of magnitude improvement of the error-correcting performance. The regularity of the BP decoder structure offers many hardware architecture choices. Silicon area, power consumption, throughput and latency can be traded to reach the optimal design points for practical use cases. A comprehensive design space exploration reveals several practical architectures at different design points. The scalability of each architecture is also evaluated based on the implementation candidates. For dynamic communication channels, such as wireless channels in the upcoming 5G applications, multiple codes of different lengths and code rates are needed to t varying channel conditions. To minimize implementation cost, a universal decoder architecture is proposed to support multiple codes through hardware reuse. A 40nm length- and rate-configurable polar decoder ASIC is demonstrated to fit various communication environments and service requirements.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/140817/1/shuangsh_1.pd

FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms

The growth of neural networks complexity has led to adopt of hardware-accelerators to cope with the computational power required by the new architectures. The possibility to adapt the network for different platforms enhanced the interests of safety-critical applications. The reliability evaluation of neural networks are still premature and requires platforms to measure the safety standards required by mission-critical applications. For this reason, the interest in studying the reliability of neural networks is growing. We propose a new approach for evaluating the resiliency of neural networks by using hybrid platforms. The approach relies on the reconfigurable hardware for emulating the target hardware platform and performing the fault injection process. The main advantage of the proposed approach is to involve the on-hardware execution of the neural network in the reliability analysis without any intrusiveness into the network algorithm and addressing specific fault models. The implementation of FireNN, the platform based on the proposed approach, is described in the paper. Experimental analyses are performed using fault injection on AlexNet. The analyses are carried out using the FireNN platform and the results are compared with the outcome of traditional software-level evaluations. Results are discussed considering the insight into the hardware level achieved using FireNN

Energy-efficient design and implementation of turbo codes for wireless sensor network

The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

Design of High Throughput Reconfigurable LDPC CODEC

Channel coding is an essential part of communication systems, which significantly reduces the error rate of receiving messages. Nowadays, iterative decoding methods play an important role in wireless communication such as 5G, Wi-Fi etc. Low-Density Parity-Check (LDPC) codes are one of the most used iterative decoding codes, which attract lots of interest in a wide range of applications. LDPC codes have a channel approaching capacity, which is practical for implementation as well. The thesis focuses on the design of high throughput reconfigurable LDPC channel codec with good performance. The main focus of this thesis is the design of a novel decoding algorithm for LDPC codes. The new decoding algorithm is configurable to adjust its performance and complexity, which is very flexible for applications. Its error correction capability is close to the sum-product algorithm but with significantly lower complexity. We further implement the LDPC encoder/decoder on FPGA, which is reconfigurable for 5G NR or user-defined LDPC codes. In particular, we apply the new decoding algorithm to the decoder and analyse its performance on hardware. Moreover, we compared the error detection performance of 5G NR CRC and LDPC Syndrome to investigate the necessity of using CRC decoding or LDPC syndrome check, or both in practical systems. At last, a 5G NR physical layer simulating SoC embedded system is built on FPGA for the verification of the encoder and decoder

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Engine monitoring based on harmonic saliencies

The fundamental frequency of the powertrain’s rotational velocity (speed) corresponds to one of the peaks in a frequency spectrum. By processing the speed signal data in the frequency domain, the signal can be decomposed into separate relevant components. Harmonic orders of the fundamental frequency correspond to various engine internal events, for example combustion events. The main objectives of this thesis are, to define relevant engine events based on their harmonic saliencies. Create a concept method for performing monitoring and speed estimation on UNIC HW and evaluate the reliability and performance of the method. First the concept method is designed with the help of Dewesoft and MATLAB softwares, which help in the process of analysing real engine speed signal data. The harmonics are also further investigated, to find if they hold relevant information that can be used in engine monitoring. After the design of the method is complete, it is then implemented on the UNIC module. When the implementation is loaded to the module testing and evaluation can begin, and it was done with a minirig. Minirig consists of a multiple UNIC system modules such as CCM-30 and COM-10. The concept method appears to be promising in calculating the engine speed. This method could be used on a real engine to provide relatively robust speed estimation and possibly replace the current methods in that area. The largest negative side of the method is the fact that in the relatively low flywheel revolutions per minute, the frequency domain data becomes unclear and difficult to perform any calculations with. Nevertheless, when calculating the speed, harmonics can also be calculated at the same time and from the same frequency domain data. This makes the concept even more appealing, because the harmonics include beneficial information about the engine’s state. The information related to harmonics can mainly be used to monitor if the engine is in normal condition, and no faults are present.Voimansiirron perustaajuus (nopeus) vastaa yhtä piikkiä taajuus spektrissä. Prosessoimalla nopeus signaalin dataa taajus alalla, signaali pystytään jakamaan eri komponentteihin, jotka sisältävät hyödyllistä tietoa. Perustaajuuden ylä-äänet vastaavat moottorissa tapahtuvia tapahtumia, esimerkiksi sytytykseen liittyviä ilmiöitä. Tämän diplomityön pää tarkoitus on määrittää olennaiset moottorin tapahtmuat perustuen niitä vastaaviin ylä-ääniin. Tehdä konsepti menetelmä, jolla voi seurata moottorin tilaa ja sen nopeutta UNIC laitteistolla. Myös menetelmän luotettavuus ja toimintakyky tulee arvoida. Aluksi konsepti menetelmä suunniteltiin Dewesoft ja MATLAB ohjelmistojen avulla. Nämä ohjelmistot auttoivat moottorin nopeus datan analysoinnissa. Ylä-ääniä tutkittiin, jotta niissä mahdollisesti olevan tiedon voisi hyödyntää moottorin seurannassa. Konsepti menetelmän suunnittelun jälkeen, menetelmää alettiin rakentamaan UNIC moduulille. Kun implementaatio tultua valmiiksi menetelmän testaus ja arviointi voitiin aloittaa. Testauksessa hyödynnettiin minirig laitteistoa, joka koostuu monesta UNIC systeemin moduulista, esimerkiksi CCM-30 ja COM-10 moduuleista. Konsepti menetelmä vaikuttaa olevan lupaava moottorin nopeuden laskemiseen. Menetelmää voisi hyödyntää oikealla moottorilla, sillä se on suhteellisen vakaa ja toimiva laskiessa nopeutta, ja menetelmä voisi mahdollisesti korvata nykyiset moottorin nopeuden laskemiseen käytetyt menetelmät. Isoin negatiivinen asia menetelmässä on se, että vauhtipyörän kierrosten ollessa todella alhaalla, taajuus-alan datasta tulee epäselvää ja sillä on vaikea tehdä kunnollisia laskelmia. Kuitenkin, kun moottorin nopeutta lasketaan voidaan samalla laskea ylä-äänet, samasta taajuus-alan datasta. Tämä tekee menetelmästä vielä vetoavamman, koska ylä-äänten datassa on hyödyllistä tietoa koskien moottorin tilaa. Ylä-äänten informaatiota voi pääasiassa käyttää hyödyksi, kun halutaan tarkistaa onko moottori normaalissa tilassa ilman vikoja