220 research outputs found
A built-in self-test technique for high speed analog-to-digital converters
Fundaรงรฃo para a Ciรชncia e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009
Circuits and algorithms for pipelined ADCs in scaled CMOS technologies
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.MIT Barker Engineering Library copy: printed in pages.Also issued printed in pages.Includes bibliographical references (leaves 179-184).CMOS technology scaling is creating significant issues for analog circuit design. For example, reduced signal swing and device gain make it increasingly difficult to realize high-speed, high-gain feedback loops traditionally used in switched capacitor circuits. This research involves two complementary methods for addressing scaling issues. First is the development of two blind digital calibration techniques. Decision Boundary Gap Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation (COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a new architecture called zero-crossing based circuits (ZCBC) that is more amenable to scaling trends. To demonstrate these circuits and algorithms, two different ADCs were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s in IBM 90nm technology. Together these techniques can be enabling technologies for both pipelined ADCs and general mixed signal design in deep sub-micron technologies.by Lane Gearle Brooks.Ph.D
Methodology for testing high-performance data converters using low-accuracy instruments
There has been explosive growth in the consumer electronics market during the last decade. As the IC industry is shifting from PC-centric to consumer electronics-centric, digital technologies are no longer solving all the problems. Electronic devices integrating mixed-signal, RF and other non-purely digital functions are becoming new challenges to the industry. When digital testing has been studied for long time, testing of analog and mixed-signal circuits is still in its development stage. Existing solutions have two major problems. First, high-performance mixed-signal test equipments are expensive and it is difficult to integrate their functions on chip. Second, it is challenging to improve the test capability of existing methods to keep up with the fast-evolving performance of mixed-signal products demanded on the market. The International Technology Roadmap for Semiconductors identified mixed-signal testing as one of the most daunting system-on-a-chip challenges;My works have been focused on developing new strategies for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Different from conventional methods that require test instruments to have better performance than the device under test, our algorithms allow the use of medium and low-accuracy instruments in testing. Therefore, we can provide practical and accurate test solutions for high-performance data converters. Meanwhile, the test cost is dramatically reduced because of the low price of such test instruments. These algorithms have the potential for built-in self-test and can be generalized to other mixed-signal circuitries. When incorporated with self-calibration, these algorithms can enable new design techniques for mixed-signal integrated circuits. Following contents are covered in the dissertation:;(1) A general stimulus error identification and removal (SEIR) algorithm that can test high-resolution ADCs using two low-linearity signals with a constant offset in between; (2) A center-symmetric interleaving (CSI) strategy for generating test signals to be used with the SEIR algorithm; (3) An architecture-based test algorithm for high-performance pipelined or cyclic ADCs using a single nonlinear stimulus; (4) Using Kalman Filter to improve the efficiency of ADC testing; and (5) A testing algorithm for high-speed high-resolution DACs using low-resolution ADCs with dithering
Recommended from our members
Correlated level shifting as a power-saving method to reduce the effects of finite DC gain and signal swing in opamps
This thesis presents methods to reduce the effects of finite opamp DC gain, output voltage swing limitations in opamps, and component mismatches. The primary contribution of this thesis is a new switched-capacitor method named correlated level shifting (CLS). CLS enables true rail-to-rail operation by storing an estimate of the desired signal on a capacitor during an "estimate" phase, and subtracting the signal from the active circuitry (typically an opamp) during a "level shift" phase. This is done within the confines of a feedback loop. The effective loop-gain is the product of the loop-gains during the estimate and level shift phases. This enables, for example, a two-stage opamp to have the accuracy of a four-stage opamp. It also enables full utilization of the power supply since the gain block's output voltage can exceed the power supply. The thesis shows that the full utilization of the power supply and the increased DC effective loop gain leads to a significant power savings compared to existing techniques.
The methods are presented in the context of pipelined analog-to-digital converters, although the methods can be used with other circuits that use opamps or are sensitive to component mismatch. An overview of the detrimental effects of reduced signal swing and low DC gain is given with an emphasis on the cost in power to correct these deficiencies when limited to existing circuit techniques. CLS is then shown to correct these deficiencies without increasing power. A detailed explanation of CLS operation is given, as are measured results from a 12-bit pipelined analog-to-digital converter that was fabricated using a 0.18ฮผ CMOS process. The results include greater than 10-bit performance with true rail-to-rail operation.
An overview of calibration is also given and the limitations are discussed. An argument is made that using CLS in addition to calibration will reduce power by increasing signal-to-noise ratio and reducing and linearizing the errors due to finite opamp gain. In addition, a method to reduce the effects of mismatch by measuring the relative size of elements is presented.
Finally, several avenues for future research into CLS are given
Estimation of Input Variable as Initial Condition of a Chaos Based Analogue to Digital Converter
A realization of an analogue-to-digital converter(ADC) with improved conversion accuracy,using the chaotic behaviour of the tent map,is presented. In this approach, the analogue input signal to be measured, termed as the initial condition is applied to a chaotic map, and the symbolic dynamics resulting from the map evolution, is used to determine the initial condition in digital form. The unimodal piecewise linear tent map (TM) has been used for this purpose, because of its property of generating uniform distribution of points and robust chaos.
Through electronic implementation of the TMit is practically impossible to produce an โidealโ TM behaviour with parameter values in the full range [0,1]. Due to component imprecision and various other factors, a non-ideal map with reduced height is observed. For such a map, converting the equivalent symbolic trajectory generated by TM iterations return erroneous results as the partitioning of the phase space embodied in the finite symbolic dynamics no longer has unique correspondence with the initial condition.
Two algorithmic solutions have been proposed to minimise the errors associated with a practical system. For one, it has been established that for a reduced-height map the partitioning will not remain of equal size. Considering that the height of the tent map used for this purpose is known from an independent but related research, a technique of partitioning the state space unevenly, depending on the map height has been proposed and has been shown that if the correct partitioning is used, the resulting symbolic dynamics again map uniquely to the initial condition.
Alternatively, it has been shown that the degree of deviation of the iterate values can be determined based on the parameter value, which in turn can be adjusted for depending on the symbolic sequence generated by the initial condition to determine the correct decimal equivalent values.
The both the approaches proved to be highly effective in obtaining a digital outcome corresponding to the initial condition using 8 symbolic iterations of the map in hardware domain, with the second approach outperforming the first in terms of accuracy, while the first method can easily be pipelined alongside generating the iterates and thus improve the speed. This development is promising because, in contrast to the commercially available ADCs, it places lower demand on the hardware resource and can be effectively implemented to give a real-time operation
FPGA๋ฅผ ์ด์ฉํ ์๊ฐ ๊ธฐ๋ฐ ๊ณ ์ง์ PET ๋ฐ์ดํฐ ์์ง ์ฅ์น
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ)--์์ธ๋ํ๊ต ๋ํ์ :์๊ณผ๋ํ ์๊ณผํ๊ณผ,2019. 8. ์ด์ฌ์ฑ.Positron emission tomography (PET) is a widely used functional imaging device for diagnosing cancer and neurodegenerative diseases. PET instrumentation studies focus on improving both spatial resolution and sensitivity to improve the lesion detectability while reducing radiation exposure to patients.
The silicon photomultiplier (SiPM) is a photosensor suitable for high-performance PET scanners owing to its compact size and fast response. However, the SiPM-based PET scanners require a large number of readout channels owing to a high level of granularity. For example, the typical whole-body PET scanners require more than 40,000 SiPM channels. Therefore, the highly integrated data acquisition (DAQ) system that can digitize a large number of SiPM signal with preserving its fast temporal response is required to develop the high-performance SiPM-based PET scanners.
Time-based signal digitization is a promising method to develop highly integrated DAQ systems owing to its simple circuitry and fast temporal response. In this thesis, studies on developing highly integrated DAQ systems using a field-programmable gate array (FPGA) were presented.
Firstly, a 10-ps time-to-digital converter (TDC) implemented within the FPGA was developed. The FPGA-TDCs suffer from the non-linearity, because FPGAs are not originally designed to implement TDC. We proposed the dual-phase sampling architecture considering the FPGA clock distribution network to mitigate the TDC non-linearity. In addition, we developed the on-the-fly calibrator that compensated the innate bin width variations without introducing the dead time.
Secondly, the time-based SiPM multiplexing and readout method was developed using the principle of the global positioning system (GPS). The signal traces connecting every SiPM to four timing channels were used to encode the position information. The position information was obtained using the innate transit time differences measured by four FPGA-TDCs. In addition, the minimal signal distortion by multiplexing circuit allowed to use a time-over-threshold (ToT) method for energy measurement after multiplexing.
Thirdly, we proposed a new FPGA-only digitizer. The programmable FPGA input/output (I/O) port was configured with stub-series terminated logic (SSTL) input receiver, and each FPGA I/O port functioned as a high-performance voltage comparator with a fast temporal response. We demonstrated that the FPGA can be used as a high-performance DAQ system by directly digitizing the time-of-flight (TOF) PET detector signals using the FPGA without any front-end electronics.
Lastly, we developed comparator-less charge-to-time converter (QTC) DAQ systems to collect data from a prototype high-resolution brain PET scanner. The energy channel consisted of a QTC combined with the SSTL input receiver of the FPGA. The timing channel was a TDC implemented within the same FPGA. The detailed structure of brain phantom was well-resolved using the developed high-resolution brain PET scanner and the highly-integrated time-based DAQ systems.์์ ์๋ฐฉ์ถ๋จ์ธต์ดฌ์ (Positron Emission Tomography; PET) ์ฅ์น๋ ์๊ณผ ์ ๊ฒฝํดํ์ฑ ์งํ์ ์์ํํ๋ ๋ฐ ๋๋ฆฌ ์ฐ์ด๋ ๊ธฐ๋ฅ ์์์ฅ์น์ด๋ค. ์ต๊ทผ PET ์ค์บ๋ ์ฐ๊ตฌ๋ ๊ณต๊ฐ ๋ถํด๋ฅ๊ณผ ์ฅ๋น ๋ฏผ๊ฐ๋๋ฅผ ๋์ฌ ๋ณ๋ณ์ ์ง๋จ์ ์ฝ๊ฒ ํ๋ฉด์ ํ์์ ๋ฐฉ์ฌ์ ํผํญ์ ์ค์ด๋ ๋ฐฉ๋ฒ์ ์ด์ ์ ๋ง์ถ๊ณ ์๋ค.
์ค๋ฆฌ์ฝ ๊ด์ฆ๋ฐฐ๊ธฐ (silicon photomultiplier; SiPM)์ ํฌ๊ธฐ๊ฐ ์๊ณ ๋ฐ์์๋๊ฐ ๋น ๋ฅด๊ธฐ ๋๋ฌธ์ ๊ณ ์ฑ๋ฅ PET ์ค์บ๋์ ์ ํฉํ ๊ด๊ฒ์ถ์์์ด๋ค. ํ์ง๋ง SiPM ๊ธฐ๋ฐ PET ์ค์บ๋๋ ๊ฐ๋ณ SiPM์ ํฌ๊ธฐ๊ฐ ์๊ธฐ ๋๋ฌธ์ ์๋ง์ ๋ฐ์ดํฐ ์์ง ์ฑ๋์ด ํ์ํ๋ค. ์๋ฅผ ๋ค์ด, ์ ์ PET ์ค์บ๋๋ฅผ SiPM์ผ๋ก ๊ตฌ์ฑํ ๊ฒฝ์ฐ 40,000๊ฐ ์ด์์ SiPM ์์๊ฐ ํ์ํ๋ค. ๋ฐ๋ผ์, SiPM์ ์ฑ๋ฅ์ ์ ์งํ๋ฉด์ ๋ค์ฑ๋ ์ ํธ ๋์งํธํ๊ฐ ๊ฐ๋ฅํ ๊ณ ์ง์ ๋ฐ์ดํฐ ์์ง์ฅ์น (data acquisition; DAQ)๊ฐ ๊ณ ์ฑ๋ฅ SiPM PET ์ค์บ๋ ๊ฐ๋ฐ์ ํ์ํ๋ค.
์๊ฐ ๊ธฐ๋ฐ ์ ํธ ๋์งํธ ๋ฐฉ๋ฒ์ ๋จ์ํ ํ๋ก์ ๋น ๋ฅธ ๋ฐ์์๋ ๋๋ถ์ ๊ณ ์ง์ DAQ ์์คํ
์ ๊ตฌํํ๋ ์ ๋งํ ๋ฐฉ๋ฒ์ด๋ค. ๋ณธ ํ์๋
ผ๋ฌธ์์๋ ํ๋ก๊ทธ๋จ ๊ฐ๋ฅ ๊ฒ์ดํธ ๋ฐฐ์ด (field-programmable gate array; FPGA)์ ์ด์ฉํ์ฌ ๊ณ ์ง์ DAQ ์์คํ
์ ๊ฐ๋ฐํ๋ ์ฐ๊ตฌ๋ด์ฉ์ ๋ค๋ฃฌ๋ค.
์ฒซ์งธ๋ก, 10 ps ์ ๋ถํด๋ฅ์ ๊ฐ๋ FPGA ๊ธฐ๋ฐ ์๊ฐ-๋์งํธ ๋ณํ๊ธฐ (time-to-digital converter; TDC)๋ฅผ ๊ฐ๋ฐํ์๋ค. FPGA๋ TDC ๊ตฌํ์ ์ํ ์ง์ ์์๊ฐ ์๋๋ฏ๋ก FPGA์ ๊ตฌํ๋ TDC๋ ์ผ๋ฐ์ ์ผ๋ก ๋น์ ํ์ฑ ๋ฌธ์ ๋ฅผ ๊ฐ์ง๋ค. ์ด๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด ๋น์ ํ์ฑ ๋ฌธ์ ๋ฅผ ์ผ๊ธฐํ๋ FPGA์ ํด๋ฝ ์ ํธ ๋ถ๋ฐฐ ๊ตฌ์กฐ๋ฅผ ๊ณ ๋ คํ์ฌ ์ด์ค ์์ ์ํ๋ง ๋ฐฉ๋ฒ์ ์ ์ํ์๋ค. ๋ํ, FPGA TDC ๊ณ ์ ์ ๋ถ๊ท ์ผํ ๋ถํด๋ฅ์ ์ธก์ ํ๊ณ ๋ณด์ํ๊ธฐ ์ํ์ฌ ์ค์๊ฐ ๋ณด์ ๊ธฐ์ ์ ๊ฐ๋ฐํ์๋ค.
๋์งธ๋ก, GPS ์๋ฆฌ๋ฅผ ์ฌ์ฉํ ์๊ฐ ๊ธฐ๋ฐ ์ ํธ ๋ถํธํ (multiplexing) ๋ฐ ์์ง ๋ฐฉ๋ฒ์ ๊ฐ๋ฐํ์๋ค. ๋ถํธํ ํ๋ก๋ SiPM์ ๋ค ๊ฐ์ ์๊ฐ ์์ง ์ฑ๋๋ก ์ฐ๊ฒฐํ ๋์ ์ผ๋ก ๊ตฌ์ฑ๋๊ณ ์์น์ ๋ณด๋ ๊ฐ SiPM์ผ๋ก๋ถํฐ ๋ค ๊ฐ์ ์๊ฐ ์์ง ์ฑ๋๊น์ง์ ๊ณ ์ ํ ๋ํ์๊ฐ ์ฐจ์ด๋ฅผ ๊ณ์ฐํด์ ์์งํ ์ ์๋ค. ๋ํ, ๊ธฐ์กด ์ ํ ๋ถ๋ฐฐ ๋ถํธํ ํ๋ก์ ๋ฌ๋ฆฌ ์ ํธ๊ฐ ์๊ณก๋์ง ์๊ธฐ ๋๋ฌธ์ ๋ฌธํฑ ์ ์ ๋ฐฉ๋ฒ (time-over-threshold; ToT) ๋ฐฉ์์ผ๋ก ์๋์ง๋ฅผ ์์งํ๋ ๊ฒ์ด ๊ฐ๋ฅํ์๋ค.
์
์งธ๋ก, FPGA๋ง์ผ๋ก ์๋ ๋ก๊ทธ ์ ํธ๋ฅผ ๋์งํธํ ํ๋ ์๋ก์ด ๋ฐฉ๋ฒ์ ๊ฐ๋ฐํ์๋ค. FPGA์ ํ๋ก๊ทธ๋จ ๊ฐ๋ฅ ์
์ถ๋ ฅํฌํธ๋ฅผ stub-series terminated logic (SSTL) ์์ ๊ธฐ๋ก ํ๋ก๊ทธ๋จํ๋ฉด, ๊ฐ๊ฐ์ FPGA ์
์ถ๋ ฅํฌํธ๊ฐ ๋น ๋ฅธ ์๊ฐ ๋ฐ์์ฑ์ ๊ฐ์ง ๊ณ ์ฑ๋ฅ ์ ์๋น๊ต๊ธฐ๋ก ๋์ํ๋ค. ๋น์ ์๊ฐ (time-of-flight; TOF) ์ธก์ ๊ฐ๋ฅ PET ๊ฒ์ถ๊ธฐ์ ์ ํธ๋ฅผ ์ ๋จํ๋ก ์์ด FPGA๋ง์ผ๋ก ๋์งํธํํ์ฌ FPGA๋ฅผ ๊ณ ์ฑ๋ฅ DAQ ์ฅ์น๋ก ์ฌ์ฉํ ์ ์์์ ์
์ฆํ์๋ค.
๋ง์ง๋ง์ผ๋ก, ๊ณต๊ฐ๋ถํด๋ฅ์ด ๋ฐ์ด๋ ๋์ ์ฉ ์ค์บ๋๋ก๋ถํฐ ๋ฐ์ดํฐ๋ฅผ ์์งํ๊ธฐ ์ํด ์ ์๋น๊ต๊ธฐ๋ฅผ ์ฌ์ฉํ์ง ์๋ ์๊ฐ ๊ธฐ๋ฐ DAQ ์ฅ์น๋ฅผ ๊ฐ๋ฐํ์๋ค. ์๋์ง ์ธก์ ์ฑ๋์ ์๊ฐ-์ ํ ๋ณํ๊ธฐ (charge-to-time converter; QTC)์ FPGA์ SSTL ์์ ๊ธฐ๋ก ๊ตฌ์ฑํ์๋ค. ์๊ฐ ์ธก์ ์ฑ๋์ FPGA ๊ธฐ๋ฐ TDC๋ก ๊ตฌ์ฑํ์๋ค. ๊ฐ๋ฐํ ๋์ ์ฉ ์ค์บ๋์ ๊ณ ์ง์ ์๊ฐ ๊ธฐ๋ฐ DAQ ์ฅ์น๋ก ํ๋ํ ๋๋ชจ์ ํฌํ
์ ์์ธํ ๊ตฌ์กฐ๋ค์ ์ ๊ตฌ๋ถ๋์๋ค.Chapter 1. Introduction 1
1.1. Background 1
1.1.1. Positron Emission Tomography 1
1.1.2. Silicon Photomultiplier 1
1.1.3. Data Acquisition System 2
1.1.4. Time-based Signal Digitization Method 3
1.2. Purpose of Research 6
Chapter 2. FPGA-based Time-to-Digital Converter 8
2.1. Background 8
2.2. Materials and Methods 9
2.2.1. Tapped-Delay-Line TDC 9
2.2.2. FPGA 11
2.2.3. Dual-Phase TDL TDC with On-the-Fly Calibrator 11
2.2.3.1. FPGA Clock Distribution Network 11
2.2.3.2. The Principle of Dual-Phase TDL TDC 14
2.2.3.3. The Principle of Pipelined On-the-Fly Calibrator 16
2.2.3.4. Implementation of Dual-Phase TDL TDC with On-the-Fly Calibrator 18
2.2.4. Experimental Setups and Data Processing 20
2.2.4.1. TDC Characteristics 21
2.2.4.2. Arrival Time Difference Measurements 22
2.3. Results 24
2.3.1. TDC Characteristics 24
2.3.2. Arrival Time Difference Measurements 25
2.4. Discussion 28
Chapter 3. Time-based Multiplexing Method 29
3.1. Background 29
3.2. Materials and Methods 30
3.2.1. Delay Grid Multiplexing 30
3.2.2. Detector for Concept Verification 32
3.2.3. Front-end Electronics 34
3.2.4. Experimental Setups 35
3.2.4.1. Data Acquisition Using the Waveform Digitizer 37
3.2.4.2. Data Acquisition Using the FPGA-TDC 37
3.2.5. Data Processing and Analysis 38
3.2.5.1. Waveform Digitizer 38
3.2.5.2. FPGA-TDC 41
3.3. Results 44
3.3.1. Waveform Digitizer 44
3.3.1.1. Waveform, Rise Time, and Decay Time 44
3.3.1.2. Flood Map 46
3.3.1.3. Energy 48
3.3.1.4. CTR 49
3.3.2. FPGA-TDC 50
3.3.2.1. ToT and Energy 50
3.3.2.2. Flood Map 51
3.3.2.3. CTR 52
3.4. Discussion 53
Chapter 4. FPGA-Only Signal Digitization Method 54
4.1. Background 54
4.2. Materials and Methods 56
4.2.1. Single-ended Memory Interface Input Receiver 56
4.2.2. SeMI Digitizer 56
4.2.3. Experimental Setup for Intrinsic Performance Characterization 59
4.2.3.1. ToT 59
4.2.3.2. Timing 60
4.2.4. Experimental Setup for Individual Signal Digitization 60
4.2.4.1. TOF PET Detector 60
4.2.4.2. Data Acquisition Using the Waveform Digitizer 61
4.2.4.3. Data Acquisition Using the SeMI Digitizer 63
4.2.4.4. Data Analysis 63
4.3. Results 64
4.3.1. Results of Intrinsic Performance Characterization 64
4.3.1.1. ToT 64
4.3.1.2. Timing 65
4.3.2. Results of Individual Signal Digitization 66
4.3.2.1. Energy 66
4.3.2.2. CTR 67
4.4. Discussion 68
Chapter 5. Comparator-less QTC DAQ Systems for High-Resolution Brain PET Scanners 70
5.1. Background 70
5.2. Materials and Methods 72
5.2.1. Brain PET Scanner 72
5.2.1.1. Block Detector 72
5.2.1.2. Sector 73
5.2.1.3. Scanner Geometry 74
5.2.2. Comparator-less QTC DAQ System 75
5.2.3. Data Acquisition Chain of Brain PET Scanner 79
5.2.4. Experimental Setups and Data Processing 79
5.2.4.1. Energy Linearity 79
5.2.4.2. Performance Evaluation of Block Detector 80
5.2.4.3. Phantom Studies 82
5.3. Results 83
5.3.1. Energy Linearity 83
5.3.2. Performance Evaluation of Block Detector 83
5.3.3. Phantom Studies 85
5.4. Discussion 87
Chapter 6. Conclusions 89
Bibliography 90
Abstract in Korean (๊ตญ๋ฌธ ์ด๋ก) 94Docto
Recommended from our members
Fully-photonic digital radio over fibre for future super-broadband access network applications
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel UniversityIn this thesis a Fully-Photonic DRoF (FP-DRoF) system is proposed for deploying of future super-broadband access networks. Digital Radio over Fibre (DRoF) is more independent of the fibre network impairments and the length of fibre than the ARoF link. In order for fully optical deployment of the signal conversion techniques in the FP-DRoF architecture, two key components an Analogue-to-Digital Converter (ADC) and a Digital-to-Analogue Converter (DAC)) for data conversion are designed and their performance are investigated whereas the physical functionality is evaluated. The system simulation results of the proposed pipelined Photonic ADC (PADC) show that the PADC has 10 GHz bandwidth around 60 GHz of sampling rate. Furthermore, by
changing the bandwidth of the optical bandpass filter, switching to another band of sampling frequency provides optimised performance condition of the PADC. The PADC has low changes on the Effective Number of Bit (ENOB) response versus analogue RF input from 1 GHz up to 22 GHz for 60 GHz sampling frequency. The proposed 8-Bit pipelined PADC performance in terms of ENOB is evaluated at 60 Gigasample/s which is about 4.1. Recently, different methods have been reported by researchers to implement Photonic DACs
(PDACs), but their aim was to convert digital electrical signals to the corresponding analogue signal by assisting the optical techniques. In this thesis, a Binary Weighted PDAC (BW-PDAC) is proposed. In this BW-PDAC, optical digital signals are fully optically converted to an analogue signal. The spurious free dynamic range at the output of the PDAC in a back-to-back deployment of the PADC and the PDAC was 26.6 dBc. For further improvement in the system performance, a 3R (Retiming, Reshaping and Reamplifying) regeneration system is proposed in this thesis. Simulation results show that for an ultrashort RZ pulse with a 5% duty cycle at 65 Gbit/s using the proposed 3R regeneration system on a link reduces rms timing jitter by 90% while the regenerated pulse eye opening height is improved by 65%. Finally, in this thesis the proposed FP-DRoF functionality is evaluated whereas its performance is investigated through a dedicated and shared fibre links. The simulation results show (in the case of low level signal to noise ratio, in comparison with ARoF through
a dedicated fibre link) that the FP-DRoF has better BER performance than the ARoF in the order of 10-20. Furthermore, in order to realize a BER about 10-25 for the ARoF, the power penalty is about 4 dBm higher than the FP-DRoF link. The simulation results demonstrate that by considering 0.2 dB/km attenuation of a standard single mode fibre, the dedicated fibre length for the FP-DRoF link can be increased to about 20 km more than the ARoF link. Moreover, for performance assessment of the proposed FP-DRoF in a shared fibre link, the BER of the FP-DRoF link is about 10-10 magnitude less than the ARoF link for -19 dBm launched power into the fibre and the power penalty of the ARoF system is 10 dBm more than the FP-DRoF link. It is significant to increase the fibre linkโs length of the FP-DRoF access network using common infrastructure. In addition, the simulation results are demonstrated that the FP-DRoF with non-uniform Wavelength Division Multiplexing (WDM) is more robust against four wave mixing impairment than the conventional WDM technique with uniform wavelength allocation and has better performance in terms of BER. It is clearly verified that the lunched power penalty at CS for DRoF link with uniform WDM techniques is about 2 dB higher than non-uniform WDM technique. Furthermore, uniform WDM method requires more bandwidth than non-uniform scheme which depends on the total number of channels and channels spacing
- โฆ