4 research outputs found

    FPGA๋ฅผ ์ด์šฉํ•œ ์‹œ๊ฐ„ ๊ธฐ๋ฐ˜ ๊ณ ์ง‘์  PET ๋ฐ์ดํ„ฐ ์ˆ˜์ง‘ ์žฅ์น˜

    Get PDF
    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ)--์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› :์˜๊ณผ๋Œ€ํ•™ ์˜๊ณผํ•™๊ณผ,2019. 8. ์ด์žฌ์„ฑ.Positron emission tomography (PET) is a widely used functional imaging device for diagnosing cancer and neurodegenerative diseases. PET instrumentation studies focus on improving both spatial resolution and sensitivity to improve the lesion detectability while reducing radiation exposure to patients. The silicon photomultiplier (SiPM) is a photosensor suitable for high-performance PET scanners owing to its compact size and fast response. However, the SiPM-based PET scanners require a large number of readout channels owing to a high level of granularity. For example, the typical whole-body PET scanners require more than 40,000 SiPM channels. Therefore, the highly integrated data acquisition (DAQ) system that can digitize a large number of SiPM signal with preserving its fast temporal response is required to develop the high-performance SiPM-based PET scanners. Time-based signal digitization is a promising method to develop highly integrated DAQ systems owing to its simple circuitry and fast temporal response. In this thesis, studies on developing highly integrated DAQ systems using a field-programmable gate array (FPGA) were presented. Firstly, a 10-ps time-to-digital converter (TDC) implemented within the FPGA was developed. The FPGA-TDCs suffer from the non-linearity, because FPGAs are not originally designed to implement TDC. We proposed the dual-phase sampling architecture considering the FPGA clock distribution network to mitigate the TDC non-linearity. In addition, we developed the on-the-fly calibrator that compensated the innate bin width variations without introducing the dead time. Secondly, the time-based SiPM multiplexing and readout method was developed using the principle of the global positioning system (GPS). The signal traces connecting every SiPM to four timing channels were used to encode the position information. The position information was obtained using the innate transit time differences measured by four FPGA-TDCs. In addition, the minimal signal distortion by multiplexing circuit allowed to use a time-over-threshold (ToT) method for energy measurement after multiplexing. Thirdly, we proposed a new FPGA-only digitizer. The programmable FPGA input/output (I/O) port was configured with stub-series terminated logic (SSTL) input receiver, and each FPGA I/O port functioned as a high-performance voltage comparator with a fast temporal response. We demonstrated that the FPGA can be used as a high-performance DAQ system by directly digitizing the time-of-flight (TOF) PET detector signals using the FPGA without any front-end electronics. Lastly, we developed comparator-less charge-to-time converter (QTC) DAQ systems to collect data from a prototype high-resolution brain PET scanner. The energy channel consisted of a QTC combined with the SSTL input receiver of the FPGA. The timing channel was a TDC implemented within the same FPGA. The detailed structure of brain phantom was well-resolved using the developed high-resolution brain PET scanner and the highly-integrated time-based DAQ systems.์–‘์ „์ž๋ฐฉ์ถœ๋‹จ์ธต์ดฌ์˜ (Positron Emission Tomography; PET) ์žฅ์น˜๋Š” ์•”๊ณผ ์‹ ๊ฒฝํ‡ดํ–‰์„ฑ ์งˆํ™˜์„ ์˜์ƒํ™”ํ•˜๋Š” ๋ฐ ๋„๋ฆฌ ์“ฐ์ด๋Š” ๊ธฐ๋Šฅ ์˜์ƒ์žฅ์น˜์ด๋‹ค. ์ตœ๊ทผ PET ์Šค์บ๋„ˆ ์—ฐ๊ตฌ๋Š” ๊ณต๊ฐ„ ๋ถ„ํ•ด๋Šฅ๊ณผ ์žฅ๋น„ ๋ฏผ๊ฐ๋„๋ฅผ ๋†’์—ฌ ๋ณ‘๋ณ€์˜ ์ง„๋‹จ์„ ์‰ฝ๊ฒŒ ํ•˜๋ฉด์„œ ํ™˜์ž์˜ ๋ฐฉ์‚ฌ์„  ํ”ผํญ์„ ์ค„์ด๋Š” ๋ฐฉ๋ฒ•์— ์ดˆ์ ์„ ๋งž์ถ”๊ณ  ์žˆ๋‹ค. ์‹ค๋ฆฌ์ฝ˜ ๊ด€์ฆ๋ฐฐ๊ธฐ (silicon photomultiplier; SiPM)์€ ํฌ๊ธฐ๊ฐ€ ์ž‘๊ณ  ๋ฐ˜์‘์†๋„๊ฐ€ ๋น ๋ฅด๊ธฐ ๋•Œ๋ฌธ์— ๊ณ ์„ฑ๋Šฅ PET ์Šค์บ๋„ˆ์— ์ ํ•ฉํ•œ ๊ด‘๊ฒ€์ถœ์†Œ์ž์ด๋‹ค. ํ•˜์ง€๋งŒ SiPM ๊ธฐ๋ฐ˜ PET ์Šค์บ๋„ˆ๋Š” ๊ฐœ๋ณ„ SiPM์˜ ํฌ๊ธฐ๊ฐ€ ์ž‘๊ธฐ ๋•Œ๋ฌธ์— ์ˆ˜๋งŽ์€ ๋ฐ์ดํ„ฐ ์ˆ˜์ง‘ ์ฑ„๋„์ด ํ•„์š”ํ•˜๋‹ค. ์˜ˆ๋ฅผ ๋“ค์–ด, ์ „์‹  PET ์Šค์บ๋„ˆ๋ฅผ SiPM์œผ๋กœ ๊ตฌ์„ฑํ•  ๊ฒฝ์šฐ 40,000๊ฐœ ์ด์ƒ์˜ SiPM ์†Œ์ž๊ฐ€ ํ•„์š”ํ•˜๋‹ค. ๋”ฐ๋ผ์„œ, SiPM์˜ ์„ฑ๋Šฅ์„ ์œ ์ง€ํ•˜๋ฉด์„œ ๋‹ค์ฑ„๋„ ์‹ ํ˜ธ ๋””์ง€ํ„ธํ™”๊ฐ€ ๊ฐ€๋Šฅํ•œ ๊ณ ์ง‘์  ๋ฐ์ดํ„ฐ ์ˆ˜์ง‘์žฅ์น˜ (data acquisition; DAQ)๊ฐ€ ๊ณ ์„ฑ๋Šฅ SiPM PET ์Šค์บ๋„ˆ ๊ฐœ๋ฐœ์— ํ•„์š”ํ•˜๋‹ค. ์‹œ๊ฐ„ ๊ธฐ๋ฐ˜ ์‹ ํ˜ธ ๋””์ง€ํ„ธ ๋ฐฉ๋ฒ•์€ ๋‹จ์ˆœํ•œ ํšŒ๋กœ์™€ ๋น ๋ฅธ ๋ฐ˜์‘์†๋„ ๋•๋ถ„์— ๊ณ ์ง‘์  DAQ ์‹œ์Šคํ…œ์„ ๊ตฌํ˜„ํ•˜๋Š” ์œ ๋งํ•œ ๋ฐฉ๋ฒ•์ด๋‹ค. ๋ณธ ํ•™์œ„๋…ผ๋ฌธ์—์„œ๋Š” ํ”„๋กœ๊ทธ๋žจ ๊ฐ€๋Šฅ ๊ฒŒ์ดํŠธ ๋ฐฐ์—ด (field-programmable gate array; FPGA)์„ ์ด์šฉํ•˜์—ฌ ๊ณ ์ง‘์  DAQ ์‹œ์Šคํ…œ์„ ๊ฐœ๋ฐœํ•˜๋Š” ์—ฐ๊ตฌ๋‚ด์šฉ์„ ๋‹ค๋ฃฌ๋‹ค. ์ฒซ์งธ๋กœ, 10 ps ์˜ ๋ถ„ํ•ด๋Šฅ์„ ๊ฐ–๋Š” FPGA ๊ธฐ๋ฐ˜ ์‹œ๊ฐ„-๋””์ง€ํ„ธ ๋ณ€ํ™˜๊ธฐ (time-to-digital converter; TDC)๋ฅผ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. FPGA๋Š” TDC ๊ตฌํ˜„์„ ์œ„ํ•œ ์ง‘์ ์†Œ์ž๊ฐ€ ์•„๋‹ˆ๋ฏ€๋กœ FPGA์— ๊ตฌํ˜„๋œ TDC๋Š” ์ผ๋ฐ˜์ ์œผ๋กœ ๋น„์„ ํ˜•์„ฑ ๋ฌธ์ œ๋ฅผ ๊ฐ€์ง„๋‹ค. ์ด๋ฅผ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•ด ๋น„์„ ํ˜•์„ฑ ๋ฌธ์ œ๋ฅผ ์•ผ๊ธฐํ•˜๋Š” FPGA์˜ ํด๋ฝ ์‹ ํ˜ธ ๋ถ„๋ฐฐ ๊ตฌ์กฐ๋ฅผ ๊ณ ๋ คํ•˜์—ฌ ์ด์ค‘ ์œ„์ƒ ์ƒ˜ํ”Œ๋ง ๋ฐฉ๋ฒ•์„ ์ œ์•ˆํ•˜์˜€๋‹ค. ๋˜ํ•œ, FPGA TDC ๊ณ ์œ ์˜ ๋ถˆ๊ท ์ผํ•œ ๋ถ„ํ•ด๋Šฅ์„ ์ธก์ •ํ•˜๊ณ  ๋ณด์ƒํ•˜๊ธฐ ์œ„ํ•˜์—ฌ ์‹ค์‹œ๊ฐ„ ๋ณด์ •๊ธฐ์ˆ ์„ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. ๋‘˜์งธ๋กœ, GPS ์›๋ฆฌ๋ฅผ ์‚ฌ์šฉํ•œ ์‹œ๊ฐ„ ๊ธฐ๋ฐ˜ ์‹ ํ˜ธ ๋ถ€ํ˜ธํ™” (multiplexing) ๋ฐ ์ˆ˜์ง‘ ๋ฐฉ๋ฒ•์„ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. ๋ถ€ํ˜ธํ™” ํšŒ๋กœ๋Š” SiPM์„ ๋„ค ๊ฐœ์˜ ์‹œ๊ฐ„ ์ˆ˜์ง‘ ์ฑ„๋„๋กœ ์—ฐ๊ฒฐํ•œ ๋„์„ ์œผ๋กœ ๊ตฌ์„ฑ๋˜๊ณ  ์œ„์น˜์ •๋ณด๋Š” ๊ฐ SiPM์œผ๋กœ๋ถ€ํ„ฐ ๋„ค ๊ฐœ์˜ ์‹œ๊ฐ„ ์ˆ˜์ง‘ ์ฑ„๋„๊นŒ์ง€์˜ ๊ณ ์œ ํ•œ ๋„ํŒŒ์‹œ๊ฐ„ ์ฐจ์ด๋ฅผ ๊ณ„์‚ฐํ•ด์„œ ์ˆ˜์ง‘ํ•  ์ˆ˜ ์žˆ๋‹ค. ๋˜ํ•œ, ๊ธฐ์กด ์ „ํ•˜ ๋ถ„๋ฐฐ ๋ถ€ํ˜ธํ™” ํšŒ๋กœ์™€ ๋‹ฌ๋ฆฌ ์‹ ํ˜ธ๊ฐ€ ์™œ๊ณก๋˜์ง€ ์•Š๊ธฐ ๋•Œ๋ฌธ์— ๋ฌธํ„ฑ ์ „์•• ๋ฐฉ๋ฒ• (time-over-threshold; ToT) ๋ฐฉ์‹์œผ๋กœ ์—๋„ˆ์ง€๋ฅผ ์ˆ˜์ง‘ํ•˜๋Š” ๊ฒƒ์ด ๊ฐ€๋Šฅํ•˜์˜€๋‹ค. ์…‹์งธ๋กœ, FPGA๋งŒ์œผ๋กœ ์•„๋‚ ๋กœ๊ทธ ์‹ ํ˜ธ๋ฅผ ๋””์ง€ํ„ธํ™” ํ•˜๋Š” ์ƒˆ๋กœ์šด ๋ฐฉ๋ฒ•์„ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. FPGA์˜ ํ”„๋กœ๊ทธ๋žจ ๊ฐ€๋Šฅ ์ž…์ถœ๋ ฅํฌํŠธ๋ฅผ stub-series terminated logic (SSTL) ์ˆ˜์‹ ๊ธฐ๋กœ ํ”„๋กœ๊ทธ๋žจํ•˜๋ฉด, ๊ฐ๊ฐ์˜ FPGA ์ž…์ถœ๋ ฅํฌํŠธ๊ฐ€ ๋น ๋ฅธ ์‹œ๊ฐ„ ๋ฐ˜์‘์„ฑ์„ ๊ฐ€์ง„ ๊ณ ์„ฑ๋Šฅ ์ „์••๋น„๊ต๊ธฐ๋กœ ๋™์ž‘ํ•œ๋‹ค. ๋น„์ •์‹œ๊ฐ„ (time-of-flight; TOF) ์ธก์ • ๊ฐ€๋Šฅ PET ๊ฒ€์ถœ๊ธฐ์˜ ์‹ ํ˜ธ๋ฅผ ์ „๋‹จํšŒ๋กœ ์—†์ด FPGA๋งŒ์œผ๋กœ ๋””์ง€ํ„ธํ™”ํ•˜์—ฌ FPGA๋ฅผ ๊ณ ์„ฑ๋Šฅ DAQ ์žฅ์น˜๋กœ ์‚ฌ์šฉํ•  ์ˆ˜ ์žˆ์Œ์„ ์ž…์ฆํ•˜์˜€๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ, ๊ณต๊ฐ„๋ถ„ํ•ด๋Šฅ์ด ๋›ฐ์–ด๋‚œ ๋‡Œ์ „์šฉ ์Šค์บ๋„ˆ๋กœ๋ถ€ํ„ฐ ๋ฐ์ดํ„ฐ๋ฅผ ์ˆ˜์ง‘ํ•˜๊ธฐ ์œ„ํ•ด ์ „์••๋น„๊ต๊ธฐ๋ฅผ ์‚ฌ์šฉํ•˜์ง€ ์•Š๋Š” ์‹œ๊ฐ„ ๊ธฐ๋ฐ˜ DAQ ์žฅ์น˜๋ฅผ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. ์—๋„ˆ์ง€ ์ธก์ • ์ฑ„๋„์€ ์‹œ๊ฐ„-์ „ํ•˜ ๋ณ€ํ™˜๊ธฐ (charge-to-time converter; QTC)์™€ FPGA์˜ SSTL ์ˆ˜์‹ ๊ธฐ๋กœ ๊ตฌ์„ฑํ•˜์˜€๋‹ค. ์‹œ๊ฐ ์ธก์ • ์ฑ„๋„์€ FPGA ๊ธฐ๋ฐ˜ TDC๋กœ ๊ตฌ์„ฑํ•˜์˜€๋‹ค. ๊ฐœ๋ฐœํ•œ ๋‡Œ์ „์šฉ ์Šค์บ๋„ˆ์™€ ๊ณ ์ง‘์  ์‹œ๊ฐ„ ๊ธฐ๋ฐ˜ DAQ ์žฅ์น˜๋กœ ํš๋“ํ•œ ๋‡Œ๋ชจ์–‘ ํŒฌํ…€์˜ ์ž์„ธํ•œ ๊ตฌ์กฐ๋“ค์€ ์ž˜ ๊ตฌ๋ถ„๋˜์—ˆ๋‹ค.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Positron Emission Tomography 1 1.1.2. Silicon Photomultiplier 1 1.1.3. Data Acquisition System 2 1.1.4. Time-based Signal Digitization Method 3 1.2. Purpose of Research 6 Chapter 2. FPGA-based Time-to-Digital Converter 8 2.1. Background 8 2.2. Materials and Methods 9 2.2.1. Tapped-Delay-Line TDC 9 2.2.2. FPGA 11 2.2.3. Dual-Phase TDL TDC with On-the-Fly Calibrator 11 2.2.3.1. FPGA Clock Distribution Network 11 2.2.3.2. The Principle of Dual-Phase TDL TDC 14 2.2.3.3. The Principle of Pipelined On-the-Fly Calibrator 16 2.2.3.4. Implementation of Dual-Phase TDL TDC with On-the-Fly Calibrator 18 2.2.4. Experimental Setups and Data Processing 20 2.2.4.1. TDC Characteristics 21 2.2.4.2. Arrival Time Difference Measurements 22 2.3. Results 24 2.3.1. TDC Characteristics 24 2.3.2. Arrival Time Difference Measurements 25 2.4. Discussion 28 Chapter 3. Time-based Multiplexing Method 29 3.1. Background 29 3.2. Materials and Methods 30 3.2.1. Delay Grid Multiplexing 30 3.2.2. Detector for Concept Verification 32 3.2.3. Front-end Electronics 34 3.2.4. Experimental Setups 35 3.2.4.1. Data Acquisition Using the Waveform Digitizer 37 3.2.4.2. Data Acquisition Using the FPGA-TDC 37 3.2.5. Data Processing and Analysis 38 3.2.5.1. Waveform Digitizer 38 3.2.5.2. FPGA-TDC 41 3.3. Results 44 3.3.1. Waveform Digitizer 44 3.3.1.1. Waveform, Rise Time, and Decay Time 44 3.3.1.2. Flood Map 46 3.3.1.3. Energy 48 3.3.1.4. CTR 49 3.3.2. FPGA-TDC 50 3.3.2.1. ToT and Energy 50 3.3.2.2. Flood Map 51 3.3.2.3. CTR 52 3.4. Discussion 53 Chapter 4. FPGA-Only Signal Digitization Method 54 4.1. Background 54 4.2. Materials and Methods 56 4.2.1. Single-ended Memory Interface Input Receiver 56 4.2.2. SeMI Digitizer 56 4.2.3. Experimental Setup for Intrinsic Performance Characterization 59 4.2.3.1. ToT 59 4.2.3.2. Timing 60 4.2.4. Experimental Setup for Individual Signal Digitization 60 4.2.4.1. TOF PET Detector 60 4.2.4.2. Data Acquisition Using the Waveform Digitizer 61 4.2.4.3. Data Acquisition Using the SeMI Digitizer 63 4.2.4.4. Data Analysis 63 4.3. Results 64 4.3.1. Results of Intrinsic Performance Characterization 64 4.3.1.1. ToT 64 4.3.1.2. Timing 65 4.3.2. Results of Individual Signal Digitization 66 4.3.2.1. Energy 66 4.3.2.2. CTR 67 4.4. Discussion 68 Chapter 5. Comparator-less QTC DAQ Systems for High-Resolution Brain PET Scanners 70 5.1. Background 70 5.2. Materials and Methods 72 5.2.1. Brain PET Scanner 72 5.2.1.1. Block Detector 72 5.2.1.2. Sector 73 5.2.1.3. Scanner Geometry 74 5.2.2. Comparator-less QTC DAQ System 75 5.2.3. Data Acquisition Chain of Brain PET Scanner 79 5.2.4. Experimental Setups and Data Processing 79 5.2.4.1. Energy Linearity 79 5.2.4.2. Performance Evaluation of Block Detector 80 5.2.4.3. Phantom Studies 82 5.3. Results 83 5.3.1. Energy Linearity 83 5.3.2. Performance Evaluation of Block Detector 83 5.3.3. Phantom Studies 85 5.4. Discussion 87 Chapter 6. Conclusions 89 Bibliography 90 Abstract in Korean (๊ตญ๋ฌธ ์ดˆ๋ก) 94Docto

    Policy Network Analysis in the Urban Planning Process

    No full text
    ๋‹ค์ˆ˜ ํ–‰์œ„์ž๋“ค๊ฐ„ ์ƒํ˜ธ์ž‘์šฉ์„ ํ†ตํ•œ ๋„์‹œ๊ณ„ํš ๊ฒฐ์ •๊ณผ์ •์„ ์˜ˆ์ธกํ•˜๊ธฐ ์œ„ํ•ด์„œ๋Š” ๊ด€๋ จ ํ–‰์œ„์ž๋“ค์ด ๋ˆ„๊ตฌ์ด๊ณ , ๊ทธ๋“ค๊ฐ„์˜ ๊ด€๊ณ„๋Š” ์–ด๋– ํ•˜๋ฉฐ, ๊ฐ๊ฐ์˜ ๋‹ค์–‘ํ•œ ๊ฐ€์น˜์™€ ์ดํ•ด๊ฐ€ ์–ด๋–ค ๋ฐฉ์‹์œผ๋กœ ์กฐ์ •๋˜๋Š” ๊ฐ€๋ฅผ ์‚ดํŽด๋ณผ ํ•„์š”๊ฐ€ ์žˆ์„ ๊ฒƒ์ด๋‹ค. ์ด์— ๋ณธ ์—ฐ๊ตฌ์—์„œ๋Š” ํ˜„๋Œ€์˜ ๋„์‹œ๊ณ„ํš๊ณผ ๊ฐ™์€ ์—ญ๋™์ ์ธ ์ •์ฑ…๊ณผ์ • ์ค‘ ๋ถ€๋ถ„์˜ ํ–‰์œ„์ž ๊ด€๊ณ„๋ฅผ ์ž˜ ๊ธฐ์ˆ ํ•ด ๋‚ผ ์ˆ˜ ์žˆ๋Š” ์ •์ฑ…๋„คํŠธ์›Œํฌ ๋ถ„์„๋ชจํ˜•์— ๊ทผ๊ฑฐํ•˜์—ฌ ์ตœ๊ทผ ์„œ์šธ์‹œ์—์„œ ์ˆ˜ํ–‰๋œ 3๊ฐ€์ง€ ๋„์‹œ๊ณ„ํš ์‚ฌ๋ก€์ธ ์ €๋ฐ€๋„์•„ํŒŒํŠธ์ง€๊ตฌ ๊ฐœ๋ฐœ๊ธฐ๋ณธ๊ณ„ํš ๋ณ€๊ฒฝ์‚ฌ๋ก€, ๊ฐœํฌํƒ์ง€๊ฐœ๋ฐœ์ง€๊ตฌ ์ง€๊ตฌ๋‹จ์œ„๊ณ„ํš๊ฒฐ์ •์‚ฌ๋ก€, ์ง€ํ•˜์ฒ 9ํ˜ธ์„  ๋„์‹œ๊ณ„ํš์‹œ์„ค ๊ฒฐ์ •์‚ฌ๋ก€ ๋“ฑ์„ ๋Œ€์ƒ์œผ๋กœ ์ •์ฑ…๊ฒฐ์ • ์ฐธ์—ฌ์ž๊ฐ„์˜ ๊ด€๊ณ„ ๋ฐ ์ƒํ˜ธ์ž‘์šฉ์„ ํŒŒ์•…ํ•˜์˜€๋‹ค. ๋ถ„์„๊ฒฐ๊ณผ ์ •์ฑ…ํ–‰์œ„์ž์˜ ์ˆ˜์™€ ๊ทœ๋ชจ, ์ฐธ์—ฌํ˜•ํƒœ์— ๋”ฐ๋ผ ๋‹ค์–‘ํ•œ ์œ ํ˜•์˜ ์ •์ฑ…๋„คํŠธ์›Œํฌ ํ˜•์„ฑ ๊ฐ€๋Šฅ์„ฑ๊ณผ ๊ฐ€๋ณ€์„ฑ์œผ๋กœ ์ธํ•ด ์ •์ฑ…๋„คํŠธ์›Œํฌ ์ œ๋„ํ™”์˜ ์ˆ˜์ค€์€ ๋‚ฎ์•˜์œผ๋ฉฐ, ์ด๋•Œ ์ •์ฑ…ํ–‰์œ„์ž๋“ค์˜ ์ฐธ์—ฌ์ˆ˜์ค€์ด๋‚˜ ์˜์‚ฌ๋ฐ˜์˜์ˆ˜์ค€์€ ์‹œ์˜ํšŒ์˜ ์ฐธ์—ฌ์™€ ์ค‘์žฌ ์—ฌ๋ถ€์— ๋”ฐ๋ผ ๋‹ฌ๋ผ์ง€๋Š” ๊ฒƒ์œผ๋กœ ๋‚˜ํƒ€๋‚ฌ๋‹ค. ๋”ฐ๋ผ์„œ ๋ฌด์—‡๋ณด๋‹ค๋„ ์‹œ์˜ํšŒ ๊ฐ™์€ ์ •์ฑ…๋„คํŠธ์›Œํฌ ๋‚ด์˜ ์—ฐ๊ฒฐ๊ณ ๋ฆฌ์กฐ์ง์˜ ์กด์žฌ์—ฌ๋ถ€๊ฐ€ ์ •์ฑ…๋„คํŠธ์›Œํฌ์˜ ํ˜•ํƒœ์— ์ค‘์š”ํ•œ ์˜ํ–ฅ์„ ๋ฏธ์น˜๋Š” ๊ฒƒ์œผ๋กœ ๋‚˜ํƒ€๋‚ฌ๋‹ค
    corecore