Electrically reconfigurable logic array

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices

Logical operations with Localized Structures

We show how to exploit excitable regimes mediated by localized structures (LS) to perform AND, OR, and NOT logical operations providing full logical functionality. Our scheme is general and can be implemented in any physical system displaying LS. In particular, LS in nonlinear photonic devices can be used for all-optical computing applications where several reconfigurable logic gates can be implemented in the transverse plane of a single device, allowing for parallel computing.Comment: 11 pages, 6 figure

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

Negative Differential Resistance, Memory and Reconfigurable Logic Functions based on Monolayer Devices derived from Gold Nanoparticles Functionalized with Electro-polymerizable Thiophene-EDOT Units

We report on hybrid memristive devices made of a network of gold nanoparticles (10 nm diameter) functionalized by tailored 3,4(ethylenedioxy)thiophene (TEDOT) molecules, deposited between two planar electrodes with nanometer and micrometer gaps (100 nm to 10 um apart), and electropolymerized in situ to form a monolayer film of conjugated polymer with embedded gold nanoparticles (AuNPs). Electrical properties of these films exhibit two interesting behaviors: (i) a NDR (negative differential resistance) behavior with a peak/valley ratio up to 17, and (ii) a memory behavior with an ON/OFF current ratio of about 1E3 to 1E4. A careful study of the switching dynamics and programming voltage window is conducted demonstrating a non-volatile memory. The data retention of the ON and OFF states is stable (tested up to 24h), well controlled by the voltage and preserved when repeating the switching cycles (800 in this study). We demonstrate reconfigurable Boolean functions in multiterminal connected NP molecule devices.Comment: Full manuscript, figures and supporting information, J. Phys. Chem. C, on line, asap (2017

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.Singapore-MIT Alliance (SMA

The development of a node for a hardware reconfigurable parallel processor

This dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication. The design of the node provided high-speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RlSC processor provided communication and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions. The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system. The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system