To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices

Agarwal, R. K.

English

NASA Technical Reports Server

ELECTRICALLYRECONFIGURABLELOGICARRAY
by
R. K. Agarwal
Assistant Professor of Electrical Engineering Tech.
AlabamaA&MUniversity
Huntsville, AL
ABSTRACT
The VLSI technology has been exploited to build more complication and
special purpose devices. Some of these devices tailored to certain complex
algorithm, systolic array processors, combinational logic, programmable logic
array and graphic display. The use of microcircuit is due to its leverage in
high integration and uniformity for mass production of simple logic or circuit
elements in the algorithm.
How does one compose the complicated systems using algorithically specialized
logic circuits or processors. One solution is to perform relational computa-
tions such as union, division and intersection directly on hardware. These
relations can be poplined efficiently on network of processor having array
configuration. These processors can be designed and implemented with few
simple cells.
In order to determine the state-of-the-art in Electrically Reconfigurable Logic
Array (ERLA), a survey of the available programmable logic array (PLA) and the
logic circuit elements used in such arrays was conducted. Based on this survey
some recommendations are made for ERLA devices.
1-2
https://ntrs.nasa.gov/search.jsp?R=19830009089 2020-03-22T00:12:05+00:00Z
LIST OFFIGURES
Figure #
I
2
3
4
S(a)
5(b)
6
.
Title
Microprocessor CPU
Programmable Logic Array
Schematic Representation of Dynamic
Two Examples of Lattice Structure
Block diagram of the R-PLA
Detail Diagram of the R-PLA
Basic Electrically Erasable Nonvalatile
Memory Element
Cell with Access Transistor and Voltage
Vanable Bootstrap Capacitor
Circuit Diagram of 1024-Bit Buried Gate
Electrically Erasable ROM
Page
I-II
I-II
1-12
1-12
1-13
1-13
1-14
1-14
1-15
1-3 /
INTRODUCTION
For the last 20 to 25 years, the semiconductor industry has been in the termoil
of innovative changes and has been the prime example of innovative excellence
in the U.S.A. Similar innovation going in the NASA programs as well as in the
electronic laboratory of the Marshall Space Flight Center. With the innovation
of integrated circuit and now with very large integrated logic array (circuit
in the range I00,000 to 1,000,000 on a single chip), new approaches have to be
invented as how to interconnect such logic array. In the order to keep the
manufacturing cost have the logic arrays are fabricated with the standard logic
circuits. Using the computer aided mask design. These arrays can be connected
to the desired configuration. With the invention of Programmable logic array,
it is deaslble to see if these logic arrays can be reprogrammed or its configura-
tion changed electrical signed in the field. The first objective of this in-
vestigation is to find on-going work in the areas of electrically reconfigurable
logic arrays (ERLA). Also study different circuit configurations and fabrication
microelectronic techniques with are presently used in programmable logic arrays,
and investigate if any of the current fabrication technique may be suitable for
'ERLA' design.
CONCLUSIONS AND RECOMMENDATIONS
The Electronically Recomfigurable Logic Arrays (ERLA) is a processed array of
microelectronic devices whose configuration (and/or connection) can be changed
by external stimuli. There are two approaches to the design of such a system.
System one where the system is partitioned into number of small processor ele-
ments (PE) also known as bit slice microprocessors whose word length could
vary by external stimuli. These PE's (or MPU's) connects through microprocessor
control units (MUC) as shown in fig. i.
The other approach is the Arrays Logic MACROS. The type of logic array considered
is the dual or folded array configuration where first one array is made up of
programmable decoders whose putput selects words in,the second array. The
programmable decode array which performs the product function known as AND
array, the second array which performs the sum function called OR array, as
shown in figure 2.
1-4
It seemssimple to use any of these two approaches to makeERLAbut in practice
designs engineer is faced with numbersof basis problems. Oneof the two main
problems are how to interconnect each cross point cell in the associative (AND)
_ogic array and the second problem is having to change the basic function of
O, 2, do't care condition at the cross points as shownin figure 2. The following
is the summaryof what is available in terms of reprogramable logic array or ERLA
and also which logic circuit configuration and fabrication technique is candidates
for ERLAat the present time.
The Restructurable VLSI is another namegiven to ERLA. The Lincoln Laboratory
of Massaschusetts Institute of Technology has been working on RVLSl. The
Lincoln Laboratory is using dynamic bonding in the Multi Project Chip (MPC)
Style of fabricating experimental NMOSintegrated circuits. Manyunrelated designs
are placed on a single die, having each with its own I/O pads. The MPCimplementa-
tion technique tends to minimize maskand wafer fabrication cost per design but
not without somedisadvantages. A schemefor the dynamic bonding of experimental
NMOStest projects has been implementedby Lincoln Laboratory as shownin fig. 3
in this scheme, all projects of a multi project die are interfaced to the same
set of physical I/O pads. The power is turned on for the selected project only.
Dynamicbonding would makeit feasible to test projects at the wafer level, simplifity
the packaging procedure, and allow all projects on a die to be tested after packag-
ing.
Redundancyis necessary in very large integrated circuits since processing these
circuits are not perfect and someof the circuity will not function. The Lincoln
Laboratory is using an approach to partition the total circuit into pieces which
can be individually tested after fabrication. These pieces are interconnected
using X-Y grid of conductors and primary interest centers on the device placed
at crossing. The Lincolm Labortaory is using lasers zappable links. The zappable
links built at Lincoln Laboratory use metal-metal structures. Data gathered at
the laboratory showedthat these failure modesinvolving metal-poly and
metal-substrate shorts in various test structures. The possibility are that these
mechanismscould be exploited to form useful links in MOSIS. Attempts were made
to use laser zapping the links but it appeared that three times the amount of
beamintensity was required to cut through poly as through metal, indicating
that it is possible to makea metal-poly link without shorting through to the
substrate.
1-5
Someof the future VLSI systems will rely on the use of ProgrammableBuilding
Blocks. Each building block consists of a set of cell design together with rules
for combining the cells into larger circuits, thus using these circuits in larger
systems. In the programmablelogic array, programmablebuilding blocks are
frequently used to implement logic design. These building blocks can be made
to change these logical functional output using electrical stimuli. These build-
ing blocks can be personalized to obtain various functions. Forter and Kung in-
troduces a new programmablebuilding block for recognition of regular languages.
The building block can be programmedfor any regular expression using a syntax
directed construction method which also allows easy and mechanical verification
of circuit properties. The recognizers madeusing these building blocks are
efficient pipeline circuits that have constant response time and avoid broadcast.
The Programmablerecognizes array (PRA)provide compact reconfigurable layouts,
(5)
requiring only nlogn area for the regular expression of length n.
Another candidate for ERLA is parallel computer. One such computer architecturel
research is going on at Purdue University called the Configurable, Highly Parallel
(Chip) computers. A Chip computer is composed of a set of homogeneous micro-
processor elements connected at regular intervals to the switches connected by
data paths to each other or to the PE's. The switch lattice is a regular structure
formed from programmable switches connected by data paths. The PE's are connected
to the switch lattice at regular intervals rather than being directly connected
to each other. External storage devices connects to the lattice at the perimeter
switches. (7) Figure 4 shows examples of switch lattices. The PE's are shown
as squares, the switches as circles and the data path as lines. The switches are
circuits rather than pcket switches. Each switch contains sufficient local memory
to store several interconnecting configuration settings. A particular setting
enables the switch to establish a direct, static connection between two or more
of its incident data paths. The design of the PE's determines the degrees to
which Chip computer is a general purpose computer, hence influenced by the intended
applications. A parallel program is considered as the composition of several
(7)
parallel algorithms each with its own processor interconnection pattern.
A programmable logic array has been recognized as an AND plane forming product
terms, followed by an OR plane combining product terms to give required output.
In other words these devices relaize combinational and sequential logic. In
order to make this reconfigurable logic array, AND and OR planes must have the
I-6
programminglinks at each cross point replaced by a link controlled from the memory
element or any other external simuli. The memoryelement at the crosspoint of
each ANDand ORgrid must also have a meansof alterning their information content
according to someexternal input. (8) Figure 5(a) and 5(b) shows diagram of a
general rewritable-programmable logic array (R-PLA, another namefor ERLA)using
conventional current modelogic (CML)memoryelement as proposed by Tanka, Ozawa
and Mori. (9) The ERLAcan be constructed by splitting a conventional randomaccess
memoryinto two sections. Henceeach cell structure of the E_ (R-PLA) is thought
as the conventional RAM,differing from the complicated cell structure is proposed
in (i0). Figure 5(a) and 5(b) shows logically as well as electrically that
Search adn Readparts of R-PLAcan perform loglc-in-memory without the use of
special ANDgates in each cell in the Readmodeand can enter a Write data from a
word direction in the Write mode. In this R-PLA, bit personalities can be easily
loaded and dynamically changedword by word to achieve specific logic function
during processing.
As mentioned earlier, there is not muchthought given to electrically Reconfigur-
able Logic Arrays, but an extensive literature is available in Alterable or
Rewritable Read-Only-Memories(ROM)or electrically reprogrammableROM(REPROM).
The semiconductor fabricated technique most promises for REPROMor ERLAis MNOS.
The devices consists of N-channel or P-channel memorytransistors with floating
(buried) gate, non-volatile memorytransistor, which enables reprogramming opera-
tion as proposed in (II). The memoryis programmedby electron injection by
junction avalanche. An internal voltage multiplication schemeusing varactor boot
strapping is used. Erasure takes place by modified Poole-Frinked conduction in
a Si3N4 of 700-A° thickness which overlays the buried (floating) gate. In this
example, standard silicon gate P-MOS processing is used (12). Bit retention is
very good even at 150°C.
The buried gate memory element, as explained in (12), after writing consists of an
"ON" P-MOS transistor with a conducting channel. After erasing, the floating
gate holds practically no negative charge, leaving the transistor in the "OFF"
state. A single transistor and an erase gate is shown in figure 6 (12) in its
simplist form. The floating gate is charged after the write pluse, resulting
in an output voltage. An erase pulse at terminal E reduces the storage change on
the floating gate below the transistor threshold voltage. Fig. 7 shows a better
form of buried-gate cell involves the addition of a boot strap variable capacitor
which is inserted between the accesses transistor and the floating gate. This
provide lower writing voltage by multiplying the voltage of the internal mode.
1-7
Fig. 8 shows a 1024 bit erasable buried gate ROMchip. To write, a bit is
selected by coincident addressing with VDDand P-terminal at -23V. Feading
is done by addressing the sameway as writing except that VDDand E-terminal
are at -15V. It appears at this time that the techniques presented represents
a reasonable approach to construct Electronically Reconfigurable logic array.
The buried (floating) gate transistor have highest promise for Electrically
Refigurable logic array. The transistor memorycell can be used in an ADD,
ORplane. The logic functions can be changedby altering cross point storage
in the matrix ANDplan as shownin Fig.g. Sametype logic or (memory)cell can
be used in PE's for the modulator approach in ERLA.
It is recommendedthat future work should be directed toward MNOSburied (floating)
gate transistor element. Also the use of cellular logic in designing specific
logic function should be implemented. The buried (floating) gate (shown in
fig. 7) can be used as an element for ANDand ORplane of macro logic array.
(Shownin fig. i). It only need five metal lines (two for x and y input, one
for erase, one _o write and one to read) to interconnect entire ANDplane.
The read output of the buried gate has to be connected as wired 'OR' on the
ANDplane before it connects to ORplane. Further study is needed to imple-
ment buried MNOSgate in the ProgrammableLogic Array (PLA) macro so that the
PLAcan be programmedelectrically in the field or run as parallel computers.
It is further recommendedthat an experimental ERLAsystem should be designed, built
and tested as a feasibility study.
I-8
i,
.
.
.
.
.
.
.
.
10.
11.
12.
13.
14.
15.
16.
REFERENCES
Scott, M.A., and Smith, K.C., "A Dynamically Reconfiguragle Microprocessor
Architecture" IEEE Trans. on Computer, Vol. 5.
Jones, J.W., "Array Logic Macros" IBM J. Res. Development, March 1975,
pp. 120-126.
Anderson, Alen H. "Restructurable VLSI Program Semi-annual Summary Report,
Lincoln Laboratory, Mass. Inst. of Tech. April 1979-March 1980, ADA09075.
Anderson, Alen H., "Restructurable VLSI Program" Semi-annual Tech, Summary
Report, Lincoln Laboratory MIT, April-September 1981 issue Jan. 1982.
Forter, J.J., and Kung, H.T., "Recognize R_gular Languages with Programmable
Building Blocks" Interim Report Dept. of Computer Science, Carnegie-Mellon
Univeristy, June 19, 1981-AD-AI04874
Snyder, Lawrence, "Overview of the CHiP Computer "VLSI 81-Book, Edited by
John P. Gray, Academic Press, pp. 237-246.
Snyder, Lawerence, "Programming Processor Interconnection Structures"
Dept. of Computer Science, Purdue University, Oct 1981, AD-AI09294.
Kinniment, D.J., "Regular Programmable Control Structures "VLSI 1981,
edited by John P. Gray, Academic Press. pp.191-202.
Tanaka, Mamoru; Ozawa, Shinju, and Mori, Shinsaku, "Rewritable Programmable
Logic Array of Current Mode Logic IEEE Trans. on computers Vol. C-30 No. 3
March 1981 pp. 229-234.
Fleisher, J., and Maissel, L.I. "An Introduction to Array Logic" IBM
J. of Res & Dev. March 1975, pp. 98-109.
WADA, Toshi, "Electrically Reprogrammable ROM Using N-channel Memory
Transistors with Floating Gate" Solid State Electronics, Vol. 20 1977
pp. 623-627.
Newgebauer, Constantine A.; Burgess, James G. and Stein, L "Electrically
Errasable Buried-Gate Nonvolatile Read-only Memory" IEEE Trans. on Elec.
Devices. Vol. ED-24 No. 5 May 1977 pp. 612-618.
Rossler, Bernard, "Electrically Erasable and Reprogrammable Read only
Memory using the N-channel SIMOS one-transistor cell "IEEE Trans on
Elec. Devices, ED-24 No. 5 May 1977, pp. 606-613.
Brewer, Joe E., "MNOS Desity Parameters" IEEE Trans. on Elec. Devices,
ED-24 No. 5 May 1977, pp. 618-625.
Wagner, Richard H. A. "The Gated-Access MNOS Memory Transistor" IEEE
Trans. on Elec. Devices. Vol. ED-27, No. 1 Jan. 1980, pp. 226-276.
Lonky, M.L.; Fagan J.L.; & Victorey J.P. "VINRAM-AN MDS/MNOS RAM" NAECON
1977, pp. 628-632.
I-9
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
LODI, Robert J. Browvicka, M.B.; Kosicki, B.B.; Pogemiller, T.A.; and Eklund,
M.V. "MNOSBORAMemoryCharacteristics "IEEE Journal of Solid State Circuits
Vol. SC-II No. 5, Oct. 1976, pp. 622-630.
Sakural, Junji, "An Experimental Study of the BO-MosDynamicRAMCell"
IEEETrans. of Electron Devices, Vol. ED-28, No. i0, Oct. 1981.
Greenwood,Ed, "VLSI Array Processor" R&DStatus Report, Jan. 11, 1982,
AD-A111986.
Wood,RoyA., "A High Density ProgrammableLogic Array Chip" IEEETrans. on
Computers, Vol. C-28, No. 9, Sept. 1979, pp. 602-607.
Smith, Kent F.; Carter, Tony M. and Hunt, Charles E. "Structured Logic Design
of Integrated Circuits Using the Storage/Logic Array (SLA)", IEEEJ. of Solid
State Circuits, Vol. SC-17, No. 2, April 1982. pp. 395-406.
Logue, J.C.; Brickman, N.F.; Howley, F.; Jones, J.W. and Wu, W.W. "Hardware
Implementation of a Small System in ProgrammableLogic Array" IBM J. of
Res. and Development, March 1975, pp. 110-119.
Patil, SuhasS. and Welch, Terry A. "A ProgrammableLogic Approach for
VLSI "IEEE Trans. on Computer, Vol. C-28, No. 9 Sept. 1979, pp. 594-601.
Mukhopadhyay,Amar "Hardware Algorithms for String Processing: IEEE.
Trans of Computer, May 1980, pp. 508-511.
Kambayashi,Yahuko "logic Design of ProgrammableLogic Arrays." IEEE
Trans of Computers. Vol. 28, No. 9, Sept. 1979, pp. 609-617.
Golden, R.L.; Latus, P.A.; and Lowy, P. "Design Automation and Programmable
Logic Array Macro". IBM J. Res. Development, Vol. 24 No.l, Jan. 1980
pp. 23-31
Mudge, Craig, J. "VLSI Chip Design at the Crossroads." VLSI 81, Academic
Press. John P. Gray, editor pp. 205-215.
Marques, Alves J. "MOSAIC: A Modular Architecture for VLSI System Circuits"
VLSI 81, AcademicPress, John P. Gray, editor, pp. 53-61.
Kautz, William H., "ProgrammableCellur Logic" Recent Developments in
Switchup Theory, Book-AmarMurkhopadhyay,editor, AcademicPress, 1971.
Chapter IX, pp. 369-421.
Goates, Gary B.; Waldron, Harvey M.; Patil, Suhar S.; Smith, Kent F. and
Tatman, JosephA., "Storage/Logic Arrays for VHSIC." Proceedings of Semi-
CustomIntegrated Circuit Technology Symposium,May 26-27, 1981
Glen W. Preston, editor, pp. 191-207.
Siskind, Jeffery Mark; Southerland, Jay Roger and Gouch, Kenneth Walter
"Generating CustomHigh Performance VLSI Designs from Succint Algorithmic
Descriptions" MIT Lincoln Laboratory, Lexington, MA, Dec. 1981.
Brewer, J.E., "MNDS-BORAMManufacturing Methods and Technology Project"
Research and DevelopmentTechnical Report, DELET-TR-80-0259,Jan. 1982
WestinghouseElectric Corp. Baltimore, MD.
I-I0
. Flr_s
I Control
Fig. I
INPUT
0
° '!.t_
X!
Fig. 2
I-ll
_m j
vim I vim I Yeom
Fig. 3
o,q
a,q
Fig. 4
1-12
_:" .... _ ......... !SE..A_C--
_j _._N
.%, ,- .... : I uu, _ 1
" I C) 1: _
"L, DRIvI: CIR J
_/2cI
, mr','_ i
, _,._ * SELECTOR 1
_%: ;.-f]w_2 - -,:.7_:-:;--
0 :::D '. ILl !
l i ..... READ P_RT
Fig. 5 (a)
_I)DP_ :,'.,
Fig.
1-13
5(b)
-_4V E
E....J L- 0
ERASE G4TE\. I SCO_
"Vw FLOAIING E
W_ /GATE1
' 1!j
I _-'J _S, L-_ I
Fig. 6
E
Y l
x_--_ o)SC,E.AT,C
-I-
W
W
v_
b) BOOTSTRAP CAPACITORh
(-) vg (+)
c) CAPACITANCE OF BOOTSTRAP
CAPACITOR AS FUNCTION OF
GATE VOLTAGE
Fig. 7
1-14
v_ov_ voo x _ASE
...... ! 1 ME.ORyCELL -_;o_-;-_
A A _ -c'_ 1_1 DI
! !;._ I, _ i I I _ r'J. J
I 32x8 i S "- i
/_ I _-_vo, ,;( i._ -- x-NORGATES----I r_, _,.._ VO, ;'
A I I
IJ/ J_ CONTROL
ImP-.......- ........._ PIN FUNCTION
) I --4-- -- ----
II _ -^ _ , A ADDRESS
li, _,'xo tI' ' : ÷ WRITE
_LL--_.................. P CLOCK
P'-_ R/W READ-WRITE
, /s
"DO I/O INPUT/OUTPUT
, _ VDO SUPPLY VOLTAGE
I
, _2x8 --T/
i
Fig. 8
1-15


Electrically reconfigurable logic array

Abstract

Similar works

Full text

Available Versions

NASA Technical Reports Server