Accurate Characterization of Silicon-On-Insulator MOSFETs for the Design of Low-Voltage, Low-Power RF Integrated Circuits

The maturation of low cost Silicon-on-Insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in-situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static small-signal model and the high-frequency noise parameters for MOSFETs. The extracted model is shown to be valid up to 40 GHz.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/44055/1/10470_2004_Article_271487.pd

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

The realization of autonomous, aircraft-based, real-time aerosol mass spectrometry in the upper troposphere and lower stratosphere

We report on the developments that enabled the field deployment of a fully automated aerosol mass spectrometer, especially designed for high-altitude measurements on unpressurized aircraft. The merits of the two main categories of real-time aerosol mass spectrometry, i.e. (a) single-particle laser desorption and ionization and (b) continuous thermal desorption and electron impact ionization of aerosols, have been integrated into one compact apparatus with the aim to perform in situ real-time analysis of aerosol chemical composition. The demonstrated instrument, named the ERICA (European Research Council Instrument for Chemical composition of Aerosols), operated successfully aboard the high-altitude research aircraft M-55 Geophysica at altitudes up to 20 km while being exposed to ambient conditions of very low atmospheric pressure and temperature. A primary goal of those field deployments was the in situ study of the Asian tropopause aerosol layer (ATAL). During 11 research flights, the instrument operated for more than 49 h and collected chemical composition information of more than 150 000 single particles combined with quantitative chemical composition analysis of aerosol particle ensembles. This paper presents in detail the technical characteristics of the main constituent parts of the instrument, as well as the design considerations for its integration into the aircraft and its autonomous operation in the upper troposphere and lower stratosphere (UTLS). Additionally, system performance data from the first field deployments of the instrument are presented and discussed, together with exemplary mass spectrometry data collected during those flights

Device and Circuit Level EMI Induced Vulnerability: Modeling and Experiments

Electro-magnetic interference (EMI) commonly exists in electronic equipment containing semiconductor-based integrated circuits (ICs). Metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the ICs may be disrupted under EMI conditions due to transient voltage-current surges, and their internal states may change undesirably. In this work, the vulnerabilities of silicon MOSFETs under EMI are studied at the device and the circuit levels, categorized as non-permanent upsets (``Soft Errors'') and permanent damages (``Hard Failures''). The Soft Errors, such as temporary bit errors and waveform distortions, may happen or be intensified under EMI, as the transient disruptions activate unwanted and highly non-linear changes inside MOSFETs, such as Impact Ionization and Snapback. The system may be corrected from the erroneous state when the EMI condition is removed. We simulate planar silicon n-type MOSFETs at the device level to study the physical mechanisms leading to or complicate the short-term, signal-level Soft Errors. We experimentally tested commercially available MOSFET devices. Not included in regular MOSFET models, exponential-like current increases as the terminal voltage increases are observed and explained using the device-level knowledge. We develop a compact Soft Error model, compatible with circuit simulators using lumped (or compact-model) components and closed-form expressions, such as SPICE, and calibrate it with our in-house experimental data using an in-house extraction technique based on the Genetic Algorithm. Example circuits are simulated using the extracted device model and under EMI-induced transient disruptions. The EMI voltage-current disruptions may also lead to permanent Hard Failures that cannot be repaired without replacement. One type of Hard Failures, the MOSFET gate dielectric (or ``oxide'') breakdown, can result in input-output relation changes and additional thermal runaway. We have fabricated individual MOSFET devices at the FabLab at the University of Maryland NanoCenter. We experimentally stress-test the fabricated devices and observe the rapid, permanent oxide breakdown. Then, we simulate a nano-scale FinFET device with ultra-thin gate oxide at the device level. Then, we apply the knowledge from our experiments to the simulated FinFET, producing a gate oxide breakdown Hard Failure circuit model. The proposed workflow enables the evaluation of EMI-induced vulnerabilities in circuit simulations before actual fabrication and experiments, which can help the early-stage prototyping process and reduce the development time

A comprehensive review on graphene nanoparticles : Preparation, properties, and applications

Graphene, with its amazing prospects and nonpareil aspects, has enticed scientists and researchers all over the globe in a significant fashion. Graphene, the super material, endlessly demonstrates some of the substantial, as well as desired, mechanical, thermal, optical, and chemical characteristics which are just about to bring about an unprecedented transformation in the science and technology field. Being derived from graphite, graphene is made of one-atom-thick, two-dimensional carbon atoms arranged in a honeycomb lattice. This Nobel-prize-winning phenomenon includes properties that may result in a new dawn of technology. Graphene, the European Union’s (EU) largest pledged project, has been extensively researched since its discovery. Several stable procedures have been developed to produce graphene nanoparticles in laboratories worldwide. Consequently, miscellaneous applications and futuristic approaches in artificial intelligence (AI)-based technology, biomedical and nanomedicine, defence and tactics, desalination, and sports are ruling over the next generation’s fast-paced world and are making the existing market competitive and transformative. This review sheds light upon the ideology of the preparation and versatile application of graphene and foretells the upcoming advancements of graphene nanoparticles with the challenges rearing ahead. The study also considers graphene nanoparticles’ diverse fields and portends their sustainability with the possibility of their acceptance in the commercial market as well as in common usage

Sustainable Transportation Program 2011 Annual Report

Highlights of selected research and development efforts at Oak Ridge National Laboratory funded by the Vehicle Technologies Program, Biomass Program, and Hydrogen and Fuel Cells Program of the Department of Energy, Office of Energy Efficiency and Renewable Energy; and the Department of Transportation

Nano-intrinsic security primitives for internet of everything

With the advent of Internet-enabled electronic devices and mobile computer systems, maintaining data security is one of the most important challenges in modern civilization. The innovation of physically unclonable functions (PUFs) shows great potential for enabling low-cost low-power authentication, anti-counterfeiting and beyond on the semiconductor chips. This is because secrets in a PUF are hidden in the randomness of the physical properties of desirably identical devices, making it extremely difficult, if not impossible, to extract them. Hence, the basic idea of PUF is to take advantage of inevitable non-idealities in the physical domain to create a system that can provide an innovative way to secure device identities, sensitive information, and their communications. While the physical variation exists everywhere, various materials, systems, and technologies have been considered as the source of unpredictable physical device variation in large scales for generating security primitives. The purpose of this project is to develop emerging solid-state memory-based security primitives and examine their robustness as well as feasibility. Firstly, the author gives an extensive overview of PUFs. The rationality, classification, and application of PUF are discussed. To objectively compare the quality of PUFs, the author formulates important PUF properties and evaluation metrics. By reviewing previously proposed constructions ranging from conventional standard complementary metal-oxide-semiconductor (CMOS) components to emerging non-volatile memories, the quality of different PUFs classes are discussed and summarized. Through a comparative analysis, emerging non-volatile redox-based resistor memories (ReRAMs) have shown the potential as promising candidates for the next generation of low-cost, low-power, compact in size, and secure PUF. Next, the author presents novel approaches to build a PUF by utilizing concatenated two layers of ReRAM crossbar arrays. Upon concatenate two layers, the nonlinear structure is introduced, and this results in the improved uniformity and the avalanche characteristic of the proposed PUF. A group of cell readout method is employed, and it supports a massive pool of challenge-response pairs of the nonlinear ReRAM-based PUF. The non-linear PUF construction is experimentally assessed using the evaluation metrics, and the quality of randomness is verified using predictive analysis. Last but not least, random telegraph noise (RTN) is studied as a source of entropy for a true random number generation (TRNG). RTN is usually considered a disadvantageous feature in the conventional CMOS designs. However, in combination with appropriate readout scheme, RTN in ReRAM can be used as a novel technique to generate quality random numbers. The proposed differential readout-based design can maintain the quality of output by reducing the effect of the undesired noise from the whole system, while the controlling difficulty of the conventional readout method can be significantly reduced. This is advantageous as the differential readout circuit can embrace the resistance variation features of ReRAMs without extensive pre-calibration. The study in this thesis has the potential to enable the development of cost-efficient and lightweight security primitives that can be integrated into modern computer mobile systems and devices for providing a high level of security

System for high and low frequency noise measurements design and semiconductor devices characterization

Orientador: Peter Jurgen TatschTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Este trabalho teve como objetivo a montagem de um sistema de caracterização de ruído de alta e de baixa freqüência, utilizando equipamentos disponíveis no Centro de Componentes Semicondutores da Unicamp. Foi montado um sistema para a caracterização do ruído de baixa freqüência em dispositivos semicondutores e desenvolveu-se um método para a análise da qualidade de interfaces e cálculo de cargas, utilizando o ruído 1/f. Na descrição do ruído em baixa freqüência é apresentado em detalhes todo o arranjo utilizado para a medição, além dos resultados da medida em transistores nMOS e CMOS do tipo p e do tipo n fabricados no Centro. Detalhes importantes sobre o cuidado com a medição, tais como a utilização de baterias para a alimentação dos dispositivos e o correto aterramento, também são esclarecidos. A faixa de freqüência utilizada vai de 1 Hz até 100 KHz. Como aplicação, a medida de ruído é utilizada como ferramenta de diagnóstico de dispositivos semicondutores. Resultados destas medidas também são apresentados. Foi desenvolvido também um sistema para a medição do ruído em alta freqüência. A caracterização teve como objetivo determinar o parâmetro conhecido como Figura de Ruído. Apresenta-se além da descrição do arranjo utilizado na medição, os equipamentos e a metodologia empregada. Em conjunto com as medidas de ruído também são apresentados os resultados das medidas de parâmetros de espalhamento. Para a validação do método de obtenção desse conjunto de medidas, um modelo de pequenos sinais de um transistor HBT, incluindo as fontes de ruído é proposto, e é apresentado o resultado entre a medição e a simulação. A faixa disponível para medida vai de 45 MHz até 30 GHz para os parâmetros de espalhamento e de 10 MHz até 1.6 GHz para medida de figura de ruídoAbstract: The main goal of this work is the development of a noise characterization system for high and low frequency measurements using equipments available at the Center for Semiconductor Components at Unicamp. A low noise characterization system for semiconductors was built and by means of 1/f noise measurement it was possible to investigate semiconductor interface condition and oxide traps density. Detailed information about the test set-up is presented along with noise measurement data for nMOS, p and n type CMOS transistors. There is also valuable information to careful conduct noise measurements, as using battery powered devices and accurate grounding procedures. The low noise set-up frequency range is from 1 Hz up to 100 KHz. Noise as a diagnostic tool for quality and reliability of semiconductor devices is also presented. Measurement data is also shown. A measurement set-up for high frequency noise characterization was developed. Measurements were carried out in order to determine the noise figure parameter (NF) of the HBT devices. Comprehensive information about the test set-up and equipments are provided. Noise data measurements and s-parameters are also presented. In order to validate the measurement procedure, a small signal model for HBT transistor including noise sources is presented. Comparisons between simulation and measured data are performed. The s-parameters frequency range is from 45 MHz to 30 GHz, and noise set-up frequency range is from 10 MHz up to 1.6 GHzDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétric

Development of InAlN HEMTs for space application

This thesis investigates the emerging InAlN high electron mobility transistor (HEMT) technology with respect to its application in the space industry. The manufacturing processes and device performance of InAlN HEMTs were compared to AlGaN HEMTs, also produced as part of this work. RF gain up to 4 GHz was demonstrated in both InAlN and AlGaN HEMTs with gate lengths of 1 μm, with InAlN HEMTs generally showing higher channel currents (~150 c.f. 60 mA/mm) but also degraded leakage properties (~ 1 x 10-4 c.f. < 1 x 10-8 A/mm) with respect to AlGaN. An analysis of device reliability was undertaken using thermal stability, radiation hardness and off-state breakdown measurements. Both InAlN and AlGaN HEMTs showed excellent stability under space-like conditions, with electrical operation maintained after exposure to 9.2 Mrad of gamma radiation at a dose rate of 6.6 krad/hour over two months and after storage at 250°C for four weeks. Furthermore a link was established between the optimisation of device performance (RF gain, power handling capabilities and leakage properties) and reliability (radiation hardness, thermal stability and breakdown properties), particularly with respect to surface passivation. Following analysis of performance and reliability data, the InAlN HEMT device fabrication process was optimised by adjusting the metal Ohmic contact formation process (specifically metal stack thicknesses and anneal conditions) and surface passivation techniques (plasma power during dielectric layer deposition), based on an existing AlGaN HEMT process. This resulted in both a reduction of the contact resistivity to around 1 x 10-4 Ω.cm2 and the suppression of degrading trap-related effects, bringing the measured gate-lag close to zero. These discoveries fostered a greater understanding of the physical mechanisms involved in device operation and manufacture, which is elaborated upon in the final chapter