Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

Early analysis of VLSI systems with packaging considerations

There is an explosive growth in the size of the VLSI (Very Large Scale Integration) systems today. Microelectronic system designers are packing millions of transistors in a single IC chip. Packaging techniques like Multi-chip module (MCM) and flip-chip bonding offer faster interconnects and IC\u27s capable of accommodating a larger number of inputs and outputs. The complexity of today\u27s designs and the availability of advanced packaging techniques call for an early analysis of the system based on estimation of system parameters to select from a wide choice of circuit partitioning, architecture alternatives and packaging options which give the best cost/performance. A procedure for the early analysis of VLSI systems under packaging considerations has been developed and implemented in this dissertation work. The early analysis tool was used to evaluate the inter-relationship between partitioning and packaging and to determine the best system design considering cost, size and delays. The functional unit level description of a 750,000-transistor MicroSparc processor was studied using an exhaustive search technique. The early analysis performed on the MicroSparc design suggested that the three chip multi-chip design using flip-chip IC\u27s interconnected on a MCM-D substrate is the most cost effective. An early bond pitch analysis performed using the tool concluded that a 250-micron bond pitch is the best choice for the multi-chip MicroSparc designs. The tool was also used to perform an early cache analysis which showed that the use of separate memory and logic processes made it feasible to design the MicroSparc design with larger cache sizes than the use of a combined logic and memory process. The designs based on the separate processes gave equivalent or better performance than the design candidates with smaller cache sizes. Future extensions of the procedure are also outlined here

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

On-chip probe metrology

The semiconductor market was valued at over $270 billion in 2007, with projections to continue steady growth [7]. Any manufacturing process of this volume is tightly controlled to ensure high efficiency, and improvements are readily sought after. Despite semiconductor fabrication process advancements allowing circuits to contain larger numbers of transistors in smaller package sizes, there has not been any significant change in the way these circuits interface with test systems before packaging. This limitation causes the area overhead occupied by circuit contacts, known as bond pads, to become increasingly costly. To amend the situation, VLSI designers have attempted to reduce bond pads size and pitch as much as possible while retaining reliable probing accuracy [15]. Currently, there is no standard solution to assess the accuracy of probe stations inline with wafer testing. As such, a balance must be struck between overhead cost of large bond pads and operational cost spent analyzing probe performance off-line. A feedback loop on probe card performance during wafer fabrication sort could allow plants to recalibrate probe cards before a yield drop is detected, thus improving yield and saving operational costs [26]. This thesis demonstrates a proof of concept design that offers a viable solution to perform probe metrology in-line with wafer-level circuit testing. A versatile circuit was designed and laid out that promises fine accuracy resolution of 3.21 μm, and fast test time of 1.25 ms per probe

Application of PEEC modeling for the development of a novel multi-gigahertz test interface with fine pitch wafer level package

Ph.DDOCTOR OF PHILOSOPH

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device

pre-printMany of the pins on a modern chip are used for power delivery. If fewer pins were used to supply the same current, the wires and pins used for power delivery would have to carry larger currents over longer distances. This results in an "IR-drop" problem, where some of the voltage is dropped across the long resistive wires making up the power delivery network, and the eventual circuits experience fluctuations in their supplied voltage. The same problem also manifests if the pin count is the same, but the current draw is higher. IR-drop can be especially problematic in 3D DRAM devices because (i) low cost (few pins and TSVs) is a high priority, (ii) 3D-stacking increases current draw within the package without providing proportionate room for more pins, and (iii) TSVs add to the resistance of the power delivery net-work. This paper is the first to characterize the relationship be- tween the power delivery network and the maximum sup ported activity in a 3D-stacked DRAM memory device. The design of the power delivery network determines if some banks can handle less activity than others. It also deter-mines the combinations of bank activities that are permissible. Both of these attributes can feed into architectural policies. For example, if some banks can handle more activities than others, the architecture benefits by placing data from high-priority threads or data from frequently accessed pages into those banks. The memory controller can also derive higher performance if it schedules requests to specific combinations of banks that do not violate the IR-drop constraint

DENSE 3D HETEROGENEOUS INTEGRATION USING SELECTIVE COBALT ALD DEPOSITION AND RECONSTITUTED TIERS

In this thesis, a new fine-pitch low-temperature bonding technology using selective Cobalt (Co) ALD deposition is presented. The benefits of selective Co ALD bonding are nanometer-scale controllability, low planarity requirement, low bonding temperature (200 oC) and potential for ultra-high-density bonds. To demonstrate selective Co ALD bonding, a Cu/Gap/Cu three-layered structure, which emulates 3D ICs stacking, is fabricated and carefully characterized. The testbed shows seamless Co interconnection between the Cu pads after Co ALD deposition for 1000 cycles. The electrical measurements demonstrate over 90% yield, which prove the Co connectivity between the Cu pads. Moreover, in this thesis, a new type of SiO2-reconstituted-tier stacking technology is proposed. The SiO2-reconstituted-tier stacking technology utilizes low-temperature ICP- PECVD SiO2 to encapsulate multi-sized chiplets. After ICP-PECVD SiO2 encapsulation, the through-oxide-vias and the pads are formed on the SiO2 to complete the reconstituted tier before stacking. Compared with conventional epoxy-molding-compound-based stacking, the SiO2 approach can have smaller loss tangent (10x), lower CTE mismatch (3x) and the higher via density (>400x). The thickness of the proposed technology can be over 10 times smaller than conventional epoxy molding. The two technologies, with further analysis and studies, open up exciting new opportunities for future 3D IC heterogeneous integration.M.S

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future