Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

Applications of formal methods in engineering

The main idea presented in this thesis is to propose and justify a general framework for the development of safety-related systems based on a selection of criticality and the required level of integrity. We show that formal methods can be practically and consistently introduced into the system design lifecycle without incurring excessive development cost. An insight into the process of generating and validating a formal specification from an engineering point of view is illustrated, in conjunction with formal definitions of specification models, safety criteria and risk assessments. Engineering specifications are classified into two main classes of systems, memoryless and memory bearing systems. Heuristic approaches for specification generation and validation of these systems are presented and discussed with a brief summary of currently available formal systems and their supporting tools. It is further shown that to efficiently address different aspects of real-world problems, the concept of embedding one logic within another mechanised logic, in order to provide mechanical support for proofs and reasoning, is practical. A temporal logic framework, which is embedded in Higher Order Logic, is used to verify and validate the design of a real-time system. Formal definitions and properties of temporal operators are defined in HOL and real-time concepts such as timing marker, interrupt and timeout are presented. A second major case study is presented on the specification a solid model for mechanical parts. This work discusses the modelling theory with set theoretic topology and Boolean operations. The theory is used to specify the mechanical properties of large distribution transformers. Associated mechanical properties such as volumetric operations are also discussed

A basis for computer-aided generation of design concepts for instrument systems

Conceptual design is the phase of design where realisable solutions are found to the functional specification of a system. At present, this is not a well supported task owing to the creativity involved in it. This thesis describes a tool which provides automated support for one of the key activities in conceptual design, the proposal of candidate solutions for analysis and evaluation, in this case to the functional specification of an instrument system, a definition of a signal transformation to be realised. The thesis defines a classification of possible functions performed by an instrument system, the associated signal transformations and the parameters which influence the transformations. A functional specification of an instrument system and a corresponding solution can both be described in terms of a configuration of these functions and the constraints on the parameters of each function in the configuration. The system provides support for the generation of solutions to a functional specification defined using this representation and a functional specification defined at different levels of abstraction can be verified by an implementation of a model which represents the signal flow through a functional configuration. The support for solution generation offered by the system is based on a systematic search of different knowledge bases which contain information on existing solution characteristics, known functional configurations, and laws of physical effects. The methods of solution generation supported include use of existing solutions, use of first principles, systematic transformation of a functional specification, or use of analogy with the functional specifications of other similar solutions

Architectural soup: a proposed very general purpose computer

Phd ThesisThis thesis is concerned with architecture for long term general purpose computers. The work is based on current trends in machine architecture and technology. Projections from these generated "Architectural Soups". An Architectural Soup has the potential to emulate many different machine architectures. The characteristics of this class of machine are, three dimensional, simple cells and a simple communications topology, which can be reconfigured at a very low level. This thesis aims to show potential usefulness and viability of machines with such capability. Methods of programming are considered, and important design issues are investigated. A specific implementation architecture is described and illustrated through simulation. An assessment is made of the architecture and of the simulator used. In addition, the implementation architecture is used as the basis for a VLSI design, which shows the simplicity of a Soup cell, and provides estimates of the possible number of cells in future machines.The Science and Engineering Research Council

Generating Programming Environments with Integrated Text and Graphics for VLSI Design Systems

The constant improvements in device integration, the development of new technologies and the emergence of new design techniques call for flexible, maintainable and robust software tools. The generic nature of compiler-compiler systems, with their semi-formal specifications, can help in the construction of those tools. This thesis describes the Wright editor generator which is used in the synthesis of language-based graphical editors (LBGEs). An LBGE is a programming environment where the programs being manipulated denote pictures. Editing actions can be specified through both textual and graphical interfaces. Editors generated by the Wright system are specified using the formalism of attribute grammars. The major example editor in this thesis, Stick-Wright, is a design entry system for the construction of VLSI circuits. Stick-Wright is a hierarchical symbolic layout editor which exploits a combination of text and graphics in an interactive environment to provide the circuit designer with a tool for experimenting with circuit topologies. A simpler system, Pict-Wright: a picture drawing system, is also used to illustrate the attribute grammar specification process. This thesis aims to demonstrate the efficacy of formal specification in the generation of software-tools. The generated system Stick-Wright shows that a text/graphic programming environment can form the basis of a powerful VLSI design tool, especially with regard to providing the designer with immediate graphical feedback. Further applications of the LBGE generator approach to system design are given for a range of VLSI design activities

Artificial intelligence methods in process plant layout

The thesis describes "Plant Layout System" or PLS, an Expert System which automates all aspects of conceptual layout of chemical process plant, from sizing equipment using process data to deriving the equipment items' elevation and plan positions. PLS has been applied to a test process of typical size and complexity and which encompasses a wide range of layout issues and problems. The thesis presents the results of the tests to show that PLS generates layouts that are entirely satisfactory and conventional from an engineering viewpoint. The major advance made during this work is the approach to layout by Expert System of any kind of process plant. The thesis describes the approach in full, together with the engineering principles which it acknowledges. Plant layout problems are computationally complex. PLS decomposes layout into a sequence of formalised steps and uses a powerful and sophisticated technique to reduce plant complexity. PLS uses constraint propagation for spatial synthesis and includes propagation algorithms developed specifically for this domain. PLS includes a novel qualitative technique to select constraints to be relaxed. A conventional frame based representation was found to be appropriate, but with procedural knowledge recorded in complex forward chaining rules with novel features. Numerous examples of the layout engineer's knowledge are included to elucidate the epistemology of the domain

Artificial intelligence methods in process plant layout

The thesis describes "Plant Layout System" or PLS, an Expert System which automates all aspects of conceptual layout of chemical process plant, from sizing equipment using process data to deriving the equipment items' elevation and plan positions. PLS has been applied to a test process of typical size and complexity and which encompasses a wide range of layout issues and problems. The thesis presents the results of the tests to show that PLS generates layouts that are entirely satisfactory and conventional from an engineering viewpoint. The major advance made during this work is the approach to layout by Expert System of any kind of process plant. The thesis describes the approach in full, together with the engineering principles which it acknowledges. Plant layout problems are computationally complex. PLS decomposes layout into a sequence of formalised steps and uses a powerful and sophisticated technique to reduce plant complexity. PLS uses constraint propagation for spatial synthesis and includes propagation algorithms developed specifically for this domain. PLS includes a novel qualitative technique to select constraints to be relaxed. A conventional frame based representation was found to be appropriate, but with procedural knowledge recorded in complex forward chaining rules with novel features. Numerous examples of the layout engineer's knowledge are included to elucidate the epistemology of the domain

Generating Circuit Tests by Exploiting Designed Behavior

This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are more readable and compact. Test programs can be constructed automatically by merging program fragments using expert-supplied goal-refinement rules and domain-independent planning techniques