Error detection and correction unit with built-in self-test capability for spacecraft applications

The objective of this project was to research and develop a 32-bit single chip Error Detection and Correction unit capable of correcting all single bit errors and detecting all double bit errors in the memory systems of a spacecraft. We designed the 32-bit EDAC (Error Detection and Correction unit) based on a modified Hamming code and according to the design specifications and performance requirements. We constructed a laboratory prototype (breadboard) which was converted into a fault simulator. The correctness of the design was verified on the breadboard using an exhaustive set of test cases. A logic diagram of the EDAC was delivered to JPL Section 514 on 4 Oct. 1988

High Performance, Point-to-Point, Transmission Line Signaling

Inter-chip signaling latency and bandwidth can be key factors limiting the performance of large VLSI systems. We present a high performance, transmission line signaling scheme for point-to-point communications between VLSI components. In particular, we detail circuitry which allows a pad driver to sense the voltage level on the attached pad during signaling and adjust the drive impedance to match the external transmission line impedance. This allows clean, reflection-free signaling despite the wide range of variations common in IC device processing and interconnect fabrication. Further, we show how similar techniques can be used to adjust the arrival time of signals to allow high signaling bandwidth despite variations in interconnect delays. This scheme employed for high performance signaling is a specific embodiment of a more general technique. Conventional electronic systems must accommodate a range of system characteristics (e.g. delay, voltage, impedance). As a result, circuit designers traditionally build large operating margins into their circuits to guarantee proper operation across all possible ranges of these characteristics. These margins are generally added at the expense of performance. The alternative scheme exemplified here is to sample these system characteristics in the device\u27s final operating environment and use this feedback to tune system operation around the observed characteristics. This tuning operation reduces the range of characteristics the system must accommodate, allowing increased performance. We briefly contrast this sampled, system-level feedback with the more conventional, fine-grained feedback employed on ICs (e.g. PLLs)

A Boundary Scan-based one-channel timing analyzer

The Boundary Scan Test infrastructure is now widely implemented in the Integrated Circuit market, especially in the microprocessor and Application-Specific Integrated Circuit arena. While the structural test of Printed Circuit Boards has been considered the driving force behind its broad acceptance, the test community has also addressed the issues of prototype debug and validation. However, the more demanding requirements associated with these issues are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 Standard, especially for debugging problems associated with real-time operation. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin, thus acting similarly to a onechannel timing analyser. This non-intrusive operating mode may also be used for field diagnosis and other online operations.info:eu-repo/semantics/publishedVersio

High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

A Spatial RAKE receiver for Real-Time UWB-IR Applications

The concept of ultra wideband impulse radio has interesting properties. The wide transmission band makes penetration through different ma­ terials better than narrow band transmission. The lack of carrier may be traded for low power solutions provided a power efficient receiver may be implemented. Unlike narrow band radio, demanding statistical computation must be carried out. This is often done in a parallel archi­ tecture. Although several portable applications are striving for higher bandwidth, there is an increasing demand for short­range low bandwidth mobile communication units. In several of these applications ultra low power is important. In addition other properties of impulse radio trans­ missions may be appreciated such as interference immunity and penet­ ration. The purpose of this thesis is to explore a low­power solution for correlator­ based impulse radio receivers. A mixed­mode parallel RAKE structure is realized in a standard 0.12 m CMOS technology. The receiver is imple­ mented as a RAKE structure combining digital shift registers with analog computation in a series of parallel taps of a synchronizing delay line. In each parallel bit stream the incoming signal is cross­correlated with a stored template. By combining a delay line and a mixed­mode correl­ ator we can explore multipath reflections in a time domain statistical computation for symbol recovery. Simulations are presented showing promising results with regard to power consumption and overall func­ tionality. Measurements are performed conforming the basic functional­ ity of the circuit

Programmable flexible cores for SoC applications

Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200

The Telecommunications and Data Acquisition Report

Deep Space Network advanced systems, very large scale integration architecture for decoders, radar interface and control units, microwave time delays, microwave antenna holography, and a radio frequency interference survey are among the topics discussed

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities