Improving Programming Support for Hardware Accelerators Through Automata Processing Abstractions

The adoption of hardware accelerators, such as Field-Programmable Gate Arrays, into general-purpose computation pipelines continues to rise, driven by recent trends in data collection and analysis as well as pressure from challenging physical design constraints in hardware. The architectural designs of many of these accelerators stand in stark contrast to the traditional von Neumann model of CPUs. Consequently, existing programming languages, maintenance tools, and techniques are not directly applicable to these devices, meaning that additional architectural knowledge is required for effective programming and configuration. Current programming models and techniques are akin to assembly-level programming on a CPU, thus placing significant burden on developers tasked with using these architectures. Because programming is currently performed at such low levels of abstraction, the software development process is tedious and challenging and hinders the adoption of hardware accelerators. This dissertation explores the thesis that theoretical finite automata provide a suitable abstraction for bridging the gap between high-level programming models and maintenance tools familiar to developers and the low-level hardware representations that enable high-performance execution on hardware accelerators. We adopt a principled hardware/software co-design methodology to develop a programming model providing the key properties that we observe are necessary for success, namely performance and scalability, ease of use, expressive power, and legacy support. First, we develop a framework that allows developers to port existing, legacy code to run on hardware accelerators by leveraging automata learning algorithms in a novel composition with software verification, string solvers, and high-performance automata architectures. Next, we design a domain-specific programming language to aid programmers writing pattern-searching algorithms and develop compilation algorithms to produce finite automata, which supports efficient execution on a wide variety of processing architectures. Then, we develop an interactive debugger for our new language, which allows developers to accurately identify the locations of bugs in software while maintaining support for high-throughput data processing. Finally, we develop two new automata-derived accelerator architectures to support additional applications, including the detection of security attacks and the parsing of recursive and tree-structured data. Using empirical studies, logical reasoning, and statistical analyses, we demonstrate that our prototype artifacts scale to real-world applications, maintain manageable overheads, and support developers' use of hardware accelerators. Collectively, the research efforts detailed in this dissertation help ease the adoption and use of hardware accelerators for data analysis applications, while supporting high-performance computation.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/155224/1/angstadt_1.pd

Dagstuhl News January - December 2006

"Dagstuhl News" is a publication edited especially for the members of the Foundation "Informatikzentrum Schloss Dagstuhl" to thank them for their support. The News give a summary of the scientific work being done in Dagstuhl. Each Dagstuhl Seminar is presented by a small abstract describing the contents and scientific highlights of the seminar as well as the perspectives or challenges of the research topic

Stream Processing using Grammars and Regular Expressions

In this dissertation we study regular expression based parsing and the use of grammatical specifications for the synthesis of fast, streaming string-processing programs. In the first part we develop two linear-time algorithms for regular expression based parsing with Perl-style greedy disambiguation. The first algorithm operates in two passes in a semi-streaming fashion, using a constant amount of working memory and an auxiliary tape storage which is written in the first pass and consumed by the second. The second algorithm is a single-pass and optimally streaming algorithm which outputs as much of the parse tree as is semantically possible based on the input prefix read so far, and resorts to buffering as many symbols as is required to resolve the next choice. Optimality is obtained by performing a PSPACE-complete pre-analysis on the regular expression. In the second part we present Kleenex, a language for expressing high-performance streaming string processing programs as regular grammars with embedded semantic actions, and its compilation to streaming string transducers with worst-case linear-time performance. Its underlying theory is based on transducer decomposition into oracle and action machines, and a finite-state specialization of the streaming parsing algorithm presented in the first part. In the second part we also develop a new linear-time streaming parsing algorithm for parsing expression grammars (PEG) which generalizes the regular grammars of Kleenex. The algorithm is based on a bottom-up tabulation algorithm reformulated using least fixed points and evaluated using an instance of the chaotic iteration scheme by Cousot and Cousot

Topics in Programming Languages, a Philosophical Analysis through the case of Prolog

[EN]Programming languages seldom find proper anchorage in philosophy of logic, language and science. is more, philosophy of language seems to be restricted to natural languages and linguistics, and even philosophy of logic is rarely framed into programming languages topics. The logic programming paradigm and Prolog are, thus, the most adequate paradigm and programming language to work on this subject, combining natural language processing and linguistics, logic programming and constriction methodology on both algorithms and procedures, on an overall philosophizing declarative status. Not only this, but the dimension of the Fifth Generation Computer system related to strong Al wherein Prolog took a major role. and its historical frame in the very crucial dialectic between procedural and declarative paradigms, structuralist and empiricist biases, serves, in exemplar form, to treat straight ahead philosophy of logic, language and science in the contemporaneous age as well. In recounting Prolog's philosophical, mechanical and algorithmic harbingers, the opportunity is open to various routes. We herein shall exemplify some: - the mechanical-computational background explored by Pascal, Leibniz, Boole, Jacquard, Babbage, Konrad Zuse, until reaching to the ACE (Alan Turing) and EDVAC (von Neumann), offering the backbone in computer architecture, and the work of Turing, Church, Gödel, Kleene, von Neumann, Shannon, and others on computability, in parallel lines, throughly studied in detail, permit us to interpret ahead the evolving realm of programming languages. The proper line from lambda-calculus, to the Algol-family, the declarative and procedural split with the C language and Prolog, and the ensuing branching and programming languages explosion and further delimitation, are thereupon inspected as to relate them with the proper syntax, semantics and philosophical élan of logic programming and Prolog

Acceleration for the many, not the few

Although specialized hardware promises orders of magnitude performance gains, their uptake has been limited by how challenging it is to program them. Hardware accelerators present challenges programmers are not used to, exposing details of the hardware that are often hidden and requiring new programming styles to use them effectively. Existing programming models often involve learning complex and hardware-specific APIs, using Domain Specific Languages (DSLs), or programming in customized assembly languages. These programming models for hardware accelerators present a significant challenge to uptake: a steep, unforgiving, and untransferable learning curve. However, programming hardware accelerators using traditional programming models presents a challenge: mapping code not written with hardware accelerators in mind to accelerators with restricted behaviour. This thesis presents these challenges in the context of the acceleration equation, and it presents solutions to it in three different contexts: for regular expression accelerators, for API-programmable accelerators (with Fourier Transforms as a key case-study) and for heterogeneous coarse-grained reconfigurable arrays (CGRAs). This thesis shows that automatically morphing software written in traditional manners to fit hardware accelerators is possible with no programmer effort and that huge potential speedups are available

Wearable, low-power CMOS ISFETs and compensation circuits for on-body sweat analysis

Complementary metal-oxide-semiconductor (CMOS) technology has been a key driver behind the trend of reduced power consumption and increased integration of electronics in consumer devices and sensors. In the late 1990s, the integration of ion-sensitive field-effect transistors (ISFETs) into unmodified CMOS helped to create advancements in lab-on-chip technology through highly parallelised and low-cost designs. Using CMOS techniques to reduce power and size in chemical sensing applications has already aided the realisation of portable, battery-powered analysis platforms, however the possibility of integrating these sensors into wearable devices has until recently remained unexplored. This thesis investigates the use of CMOS ISFETs as wearable electrochemical sensors, specifically for on-body sweat analysis. The investigation begins by evaluating the ISFET sensor for wearable applications, identifying the key advantages and challenges that arise in this pursuit. A key requirement for wearable devices is a low power consumption, to enable a suitable operational life and small form factor. From this perspective, ISFETs are investigated for low power operation, to determine the limitations when trying to push down the consumption of individual sensors. Batteryless ISFET operation is explored through the design and implementation of a 0.35 \si{\micro\metre} CMOS ISFET sensing array, operating in weak-inversion and consuming 6 \si{\micro\watt}. Using this application-specific integrated circuit (ASIC), the first ISFET array powered by body heat is demonstrated and the feasibility of using near-field communication (NFC) for wireless powering and data transfer is shown. The thesis also presents circuits and systems for combatting three key non-ideal effects experienced by CMOS ISFETs, namely temperature variation, threshold voltage offset and drift. An improvement in temperature sensitivity by a factor of three compared to an uncompensated design is shown through measured results, while adding less than 70 \si{\nano\watt} to the design. A method of automatically biasing the sensors is presented and an approach to using spatial separation of sensors in arrays in applications with flowing fluids is proposed for distinguishing between signal and sensor drift. A wearable device using the ISFET-based system is designed and tested with both artificial and natural sweat, identifying the remaining challenges that exist with both the sensors themselves and accompanying components such as microfluidics and reference electrode. A new ASIC is designed based on the discoveries of this work and aimed at detecting multiple analytes on a single chip. %Removed In the latter half of the thesis, Finally, the future directions of wearable electrochemical sensors is discussed with a look towards embedded machine learning to aid the interpretation of complex fluid with time-domain sensor arrays. The contributions of this thesis aim to form a foundation for the use of ISFETs in wearable devices to enable non-invasive physiological monitoring.Open Acces

An industrialized microprocessor system

The aim of this project is to design and build an industrialized microprocessor system capable of testing the limits and capabilities of microprocessors in the industrial process control world. The system must be capable of operating in a data logging or control or supervisory capacity. The system consists of a ruggerdized, electrically isolated unit, designed on a "black box" principle, with minimum operator controls. It is housed in a sealed crate with internal access via rows of input and output plugs and connecters. The system has been designed on a modular basis in order to simplify expansion. It can be operated as a small dedicated controller or expanded by the addition of memory and/or industrial I/O modules to its full capacity. The system is based on an INTEL 8080 microprocessor. The industrial interface consists of electrically isolated analog and digital input and output modules which can be selected under program control. There are also up to 64 asynchronous priority encoded alarm channels that can interrupt the control sequence at any time should an alarm condition arise. For debugging hardware and software a plug-on front panel unit is provided