Analysis and Characterization of Single-Poly Floating Gate Devices in 0.35um PDSOI Process

The purpose of this thesis is to demonstrate a single-poly Floating Gate Device (FGD) in 0.35 m Partially Depleted Silicon On Insulator (PDSOI) process for use in analog circuits for post process trimming. Floating gate devices with different aspect ratios have been fabricated to facilitate this behavioral study in PDSOI process. Fundamentals of floating gate devices, the advantages and disadvantages of PDSOI compared to bulk CMOS with respect to single-poly floating gate devices are discussed. Various experiments on behavior and performance of threshold voltage have been conducted and its variation with programming/erasing time and amplitude has been analyzed. The single-poly FGD’s on-resistance variation and hysteresis behavior with threshold voltage has been documented. A mathematical relation between FGD’s on-resistance and threshold voltage has been experimentally derived. Intrinsic data retention has been estimated through extrapolation of experimental data. A process independent MATLAB simulation model has been successfully developed for understanding the threshold voltage time dependence characteristics. And finally, this work has shown that programmable or post-process trimmable analog circuits can be implemented in SOI using single-poly FGDs as programmable resistive elements. A SOI programmable beta-multiplier current reference has been successfully demonstrated using the singlepoly FGD as a resistive element

An FPGA Based Testbench for Reliability and Endurance Characterization of Nonvolatile Memory

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJet Propulsion Laboratory / JPL 122991Ope

Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage

We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media

High dielectric constant materials in SONOS-type non- volatile memory structures

Ph.DDOCTOR OF PHILOSOPH

High performance floating gate memories using graphene as charge storage medium and atomic layer deposited high-k dielectric layers as tunnel barrier

Ankara : Materials Science and Nanotechnology Program of the Graduate School of Engineering and Science of Bilkent Univerity, 2013.Thesis (Master's) -- Bilkent University, 2013.Includes bibliographical references leaves 87-98.With the ongoing development in portable electronic devices, low power consumption, improved data retention rate and higher operation speed are the merits demanded by modern non-volatile memory technology. Flash memory devices with discrete charge-trapping media are regarded as an alternative solution to conventional floating gate technology. Flash memories utilizing Sinitride as charge storage media dominate due to enhanced endurance, better scaling capability and simple fabrication. The use of high-k dielectrics as tunnel layer and control layer is also crucial in charge-trap flash memory devices since they allow further scaling and enhanced charge injection without data retention degradation. Atomic layer deposition (ALD) is a powerful technique for the growth of pinhole-free high-k dielectrics with precisely controlled thickness and high conformality. The application of graphene as charge trapping medium in flash memory devices is promising to obtain improved charge storage capability with miniaturization. Graphene acts as an effective charge storage medium due to high density of states in deep energy levels. In this thesis, we fabricate graphene flash memory devices with ALD-grown HfO2/AlN as tunnel layer and Al2O3 as control layer. Graphene oxide nanosheets are derived from the acid exfoliation of natural graphite by Hummers Method. The graphene layer is obtained by spin-coating of water soluble graphene oxide suspension followed by a thermal annealing process. Memory performance including hysteresis window, data retention rate and program transient characteristics for both electron and hole storage mechanisms are determined by performing high frequency capacitance-voltage measurements. For comparing the memory effect of graphene on device performance, we also fabricate and characterize identical flash capacitors with Si-rich SiN layer as charge storage medium and HfO2 as tunnel oxide layer. The Si-nitride films are deposited with high SiH4/NH3 gas flow ratio by plasma-enhanced chemical vapor deposition system. Graphene flash memory devices exhibit superior memory performance. Compared with Si-nitride based cells, hysteresis window, retention performance and programming speed are both significantly enhanced with the use of graphene. For electron storage, graphene flash memory provides a saturated flat band shift of 1.2 V at a write-pulse duration of 100 ns with a voltage bias of 5 V. The high density of states and high work function of graphene improve the memory performance, leading to increased charge storage capability, enhanced retention rate and faster programming operation at low voltages. The use of graphene as charge storage medium and ALD-grown high-k dielectrics as tunnel and control layers improves the existing flash technology and satisfies the requirements including scalability, at least 10-year retention, low voltage operation, faster write performance and CMOS-compatible fabrication.Kocaay, DenizM.S