349 research outputs found
Novel Bonding technologies for wafer-level transparent packaging of MOEMS
Depending on the type of Micro-Electro-Mechanical System (MEMS), packaging
costs are contributing up to 80% of the total device cost. Each MEMS device
category, its function and operational environment will individually dictate
the packaging requirement. Due to the lack of standardized testing procedures,
the reliability of those MEMS packages sometimes can only be proven by taking
into consideration its functionality over lifetime. Innovation with regards to
cost reduction and standardization in the field of packaging is therefore of
utmost importance to the speed of commercialisation of MEMS devices. Nowadays
heavily driven by consumer applications the MEMS device market is forecasted to
enjoy a compound annual growth rate (CAGR) above 13%, which is when compared to
the IC device market, an outstanding growth rate. Nevertheless this forecasted
value can drift upwards or downwards depending on the rate of innovation in the
field of packaging. MEMS devices typically require a specific fabrication
process where the device wafer is bonded to a second wafer which effectively
encapsulates the MEMS structure. This method leaves the device free to move
within a vacuum or an inert gas atmosphere.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/EDA-Publishing
Heterogeneous 2.5D integration on through silicon interposer
© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity
Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects
New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects.
The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud.
The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies
Photonic packaging: transforming silicon photonic integrated circuits into photonic devices
Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved
Co-Package Technology Platform for Low-Power and Low-Cost Data Centers
We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum dot MBE growth, characterization and gain stack designs were developed. Packaging of these 2D photonic arrays in a chiplet configuration was demonstrated using a vertical integration approach in which the optical interconnect matrix was flip-chip assembled on top of a CMOS mimic chip with 2D vertical fiber coupling. The optical chiplet was further assembled on a substrate to facilitate integration with the multi-chip module of the co-packaged system with a switch surrounded by several such optical chiplets. We summarize the features of the L3MATRIX co-package technology platform and its holistic toolbox of technologies to address the next generation of computing challenges
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
Decades of progress in energy-efficient and low-power design have
successfully reduced the operational carbon footprint in the semiconductor
industry. However, this has led to an increase in embodied emissions,
encompassing carbon emissions arising from design, manufacturing, packaging,
and other infrastructural activities. While existing research has developed
tools to analyze embodied carbon at the computer architecture level for
traditional monolithic systems, these tools do not apply to near-mainstream
heterogeneous integration (HI) technologies. HI systems offer significant
potential for sustainable computing by minimizing carbon emissions through two
key strategies: ``reducing" computation by reusing pre-designed chiplet IP
blocks and adopting hierarchical approaches to system design. The reuse of
chiplets across multiple designs, even spanning multiple generations of
integrated circuits (ICs), can substantially reduce embodied carbon emissions
throughout the operational lifespan. This paper introduces a carbon analysis
tool specifically designed to assess the potential of HI systems in
facilitating greener VLSI system design and manufacturing approaches. The tool
takes into account scaling, chiplet and packaging yields, design complexity,
and even carbon overheads associated with advanced packaging techniques
employed in heterogeneous systems. Experimental results demonstrate that HI can
achieve a reduction of embodied carbon emissions up to 70\% compared to
traditional large monolithic systems. These findings suggest that HI can pave
the way for sustainable computing practices, contributing to a more
environmentally conscious semiconductor industry.Comment: Under review at HPCA2
High Efficiency Polymer based Direct Multi-jet Impingement Cooling Solution for High Power Devices
Liquid jet impingement cooling is an efficient cooling technique where the
liquid coolant is directly ejected from nozzles on the chip backside resulting
in a high cooling efficiency due to the absence of the TIM and the lateral
temperature gradient. In literature, several Si-fabrication based impingement
coolers with nozzle diameters of a few distributed returns or combination of
micro-channels and impingement nozzles. The drawback of this Si processing of
the cooler is the high fabrication cost. Other fabrication methods for nozzle
diameters for ceramic and metal. Low cost fabrication methods, including
injection molding and 3D printing have been introduced for much larger nozzle
diameters (mm range) with larger cooler dimensions. These dimensions and
processes are however not compatible with the chip packaging process flow. This
PhD focuses on the modeling, design, fabrication and characterization of a
micro-scale liquid impingement cooler using advanced, yet cost efficient,
fabrication techniques. The main objectives are: (a) development of a modeling
methodology to optimize the cooler geometry; (b) exploring low cost fabrication
methods for the package level impingement jet cooler; (c) experimental thermal
and hydraulic characterization and analysis of the fabricated coolers; (d)
applying the direct impingement jet cooling solutions to different
applications
Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications
Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung
List of symbols and abbreviations
Acknowledgement
1. Introduction
2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias
3. Fabrication of BiCMOS & Silicon Interposer with TSVs
4. Characterization of BiCMOS Embedded Through-Silicon Vias
5. Applications
6. Conclusion and Future Work
7. Appendix
8. Publications & Patents
9. Bibliography
10. List of Figures and Table
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