Grid infrastructures for the electronics domain: requirements and early prototypes from an EPSRC pilot project

The fundamental challenges facing future electronics design is to address the decreasing – atomistic - scale of transistor devices and to understand and predict the impact and statistical variability these have on design of circuits and systems. The EPSRC pilot project “Meeting the Design Challenges of nanoCMOS Electronics” (nanoCMOS) which began in October 2006 has been funded to explore this space. This paper outlines the key requirements that need to be addressed for Grid technology to support the various research strands in this domain, and shows early prototypes demonstrating how these requirements are being addressed

The 2019 materials by design roadmap

Advances in renewable and sustainable energy technologies critically depend on our ability to design and realize materials with optimal properties. Materials discovery and design efforts ideally involve close coupling between materials prediction, synthesis and characterization. The increased use of computational tools, the generation of materials databases, and advances in experimental methods have substantially accelerated these activities. It is therefore an opportune time to consider future prospects for materials by design approaches. The purpose of this Roadmap is to present an overview of the current state of computational materials prediction, synthesis and characterization approaches, materials design needs for various technologies, and future challenges and opportunities that must be addressed. The various perspectives cover topics on computational techniques, validation, materials databases, materials informatics, high-throughput combinatorial methods, advanced characterization approaches, and materials design issues in thermoelectrics, photovoltaics, solid state lighting, catalysts, batteries, metal alloys, complex oxides and transparent conducting materials. It is our hope that this Roadmap will guide researchers and funding agencies in identifying new prospects for materials design

Integrating security solutions to support nanoCMOS electronics research

The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative electronics research across multiple institutions in the UK with especially strong industrial and commercial involvement. Unlike other domains, the electronics industry is driven by the necessity of protecting the intellectual property of the data, designs and software associated with next generation electronics devices and therefore requires fine-grained security. Similarly, the project also demands seamless access to large scale high performance compute resources for atomic scale device simulations and the capability to manage the hundreds of thousands of files and the metadata associated with these simulations. Within this context, the project has explored a wide range of authentication and authorization infrastructures facilitating compute resource access and providing fine-grained security over numerous distributed file stores and files. We conclude that no single security solution meets the needs of the project. This paper describes the experiences of applying X.509-based certificates and public key infrastructures, VOMS, PERMIS, Kerberos and the Internet2 Shibboleth technologies for nanoCMOS security. We outline how we are integrating these solutions to provide a complete end-end security framework meeting the demands of the nanoCMOS electronics domain

Wide and ultra-wide bandgap oxides : where paradigm-shift photovoltaics meets transparent power electronics

Oxides represent the largest family of wide bandgap (WBG) semiconductors and also offer a huge potential range of complementary magnetic and electronic properties, such as ferromagnetism, ferroelectricity, antiferroelectricity and high-temperature superconductivity. Here, we review our integration of WBG and ultra WBG semiconductor oxides into different solar cells architectures where they have the role of transparent conductive electrodes and/or barriers bringing unique functionalities into the structure such above bandgap voltages or switchable interfaces. We also give an overview of the state-of-the-art and perspectives for the emerging semiconductor β- GaO, which is widely forecast to herald the next generation of power electronic converters because of the combination of an UWBG with the capacity to conduct electricity. This opens unprecedented possibilities for the monolithic integration in solar cells of both self-powered logic and power electronics functionalities. Therefore, WBG and UWBG oxides have enormous promise to become key enabling technologies for the zero emissions smart integration of the internet of things

Nanotechnology for catalysis and solar energy conversion

This roadmap on Nanotechnology for Catalysis and Solar Energy Conversion focuses on the application of nanotechnology in addressing the current challenges of energy conversion: 'high efficiency, stability, safety, and the potential for low-cost/scalable manufacturing' to quote from the contributed article by Nathan Lewis. This roadmap focuses on solar-to-fuel conversion, solar water splitting, solar photovoltaics and bio-catalysis. It includes dye-sensitized solar cells (DSSCs), perovskite solar cells, and organic photovoltaics. Smart engineering of colloidal quantum materials and nanostructured electrodes will improve solar-to-fuel conversion efficiency, as described in the articles by Waiskopf and Banin and Meyer. Semiconductor nanoparticles will also improve solar energy conversion efficiency, as discussed by Boschloo et al in their article on DSSCs. Perovskite solar cells have advanced rapidly in recent years, including new ideas on 2D and 3D hybrid halide perovskites, as described by Spanopoulos et al 'Next generation' solar cells using multiple exciton generation (MEG) from hot carriers, described in the article by Nozik and Beard, could lead to remarkable improvement in photovoltaic efficiency by using quantization effects in semiconductor nanostructures (quantum dots, wires or wells). These challenges will not be met without simultaneous improvement in nanoscale characterization methods. Terahertz spectroscopy, discussed in the article by Milot et al is one example of a method that is overcoming the difficulties associated with nanoscale materials characterization by avoiding electrical contacts to nanoparticles, allowing characterization during device operation, and enabling characterization of a single nanoparticle. Besides experimental advances, computational science is also meeting the challenges of nanomaterials synthesis. The article by Kohlstedt and Schatz discusses the computational frameworks being used to predict structure–property relationships in materials and devices, including machine learning methods, with an emphasis on organic photovoltaics. The contribution by Megarity and Armstrong presents the 'electrochemical leaf' for improvements in electrochemistry and beyond. In addition, biohybrid approaches can take advantage of efficient and specific enzyme catalysts. These articles present the nanoscience and technology at the forefront of renewable energy development that will have significant benefits to society

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Prediction Of Electrostatic Discharge Soft Error On Two-Way Radio Using Simulation And Immunity Scanning Technique

Electrostatic discharge (ESD) is a major cause of failures and malfunctions in two-way communication radio. Soft error failures like logic error, latch-up and wrong reset can occur as a result of the excessive ESD. It is a well-known fact that the Complementary Metal-Oxide- Semiconductor (CMOS) devices are more susceptible to ESD. The failure of CMOS ICs due to ESD can also cause radio to reset or shutdown completely. Presently the failures are detected after the radio is built and tested only. In this research, new methodology is developed to assess the ESD risk of two-way radio at circuit level. Poynting vector is used to calculate the incident power received by susceptible integrated circuit during ESD. In doing so the two-way radio is modeled in 3-D using the IEC 61000-4-2 standard. The result provides a graphical means to visualize the propagation of ESD current in Printed Circuit Board (PCB) and ground plane. Time-weighted average power density (Stwa) calculated as a cross product between E-field and H-field was used extensively in the modeling, from which a maximum limit of 3.7 W=m2, Stwa was established for predicting ESD failures. It was observed that results obtained through computer simulation agree well with measured values within some tolerance limit. It was also discovered that the improved radio with metal bar is well above this limit compared to the original radio. It is also predicted that the soft error due to ESD would occur at 11 kV and 8 kV for improved and original radio respectively. Results from this study provide a new scheme for engineers to assess ESD risk of two-way radio at PCB level. Identifying most susceptible component to ESD allows radio failures to be addressed adequately before mass production

Field-Effect Transistors based on 2-D Materials: a Modeling Perspective

Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity as its Silicon counterpart, device simulation can be of great help to predict the ultimate performance of 2D FETs and provide experimentalists with reliable design guidelines. In this paper, an ab initio modelling approach dedicated to well-known and exotic 2D materials is presented and applied to the simulation of various components, from thermionic to tunnelling transistors based on mono- and multi-layer channels. Moreover, the physics of metal - 2D semiconductor contacts is revealed and the importance of different scattering sources on the mobility of selected 2D materials is discussed. It is expected that modeling frameworks similar to the one described here will not only accompany future developments of 2D devices, but will also enable them