Half adder capabilities of a coupled quantum dot device

We gratefully acknowledge nancial support from the European Union (FPVII, 2007- 2013) under grant agreement no 256959 NANOPOWER and grant agreement no 318287 LANDAUER as well as from the state of Bavaria.In this paper we demonstrate two realizations of a half adder based on a voltage-rectifying mechanism involving two Coulomb-coupled quantum dots. First, we examine the ranges of operation of the half adder's individual elements, the AND and XOR gates, for a single rectifying device. It allows a switching between the two gates by a control voltage and thus enables a clocked half adder operation. The logic gates are shown to be reliably operative in a broad noise amplitude range with negligible error probabilities. Subsequently, we study the implementation of the half adder in a combined double-device consisting of two individually tunable rectifiers. We show that this double device allows a simultaneous operation of both relevant gates at once. The presented devices draw their power solely from electronic fluctuations and are therefore an advancement in the field of energy efficient and autonomous electronics.PostprintPeer reviewe

Método de suavização de imagem baseado num modelo variacional paralelizado em arquitetura CUDA

O aumento constante da velocidade de cálculo dos processadores tem sido uma grande aliada no desenvolvimento de áreas da ciência que exigem processamento de alto desempenho. Associado ao aumento dos recursos computacionais, tem-se presenciado um aumento no emprego de técnicas de computação paralela, no intuito de explorar ao máximo a capacidade de processamento das arquiteturas multiprocessador. No entanto, o custo financeiro para aquisição de hardware para computação paralela não é baixo, implicando assim aa busca de alternativas. A arquitetura GPGPU (General Purpose Computing on Graphics Processing Unit), torna-se uma opção de baixo custo sem comprometer o poder de processamento necessário. Neste trabalho, esta arquitetura é empregada na paralelização de um método de suavização de imagem baseado num modelo variacional, aplicado em sequências de imagens de ultra-sonografia. Os resultados obtidos são promissores, permitindo um ganho de tempo computacional considerável

ORGANIZATION OF MEMORY CHIPS IN MEMORY SYSTEMS THAT HAVE WORD SIZE WIDER THAN 8-BIT

This paper presents a method to organize memory chips when they are used to build memory systems that have word size wider than 8-bit. Most memory chips have 8-bit word size. When the memory system has to be built from several memory chips of various sizes, this method gives all possible organizations of these chips in the memory system. This paper also suggests a precise definition of the term “memory bank” that is usually used in memory systems. Finally, an illustrative design problem was taken to illustrate the presented method practicall

Field-Configurable GPU

Nesta dissertação pretende-se desenvolver uma arquitetura de processamento dedicada destinada à aceleração de aplicações específicas, inspirada na estrutura de unidades de processamento do tipo GPU. A unidade de processamento deverá ser programável e configurável para os requisitos de aplicações específicas, sendo adaptada aos tipos e à quantidade de recursos lógicos disponíveis num dispositivo FPGA selecionado. Pretende-se que o acelerador consiga tirar o máximo partido dos recursos disponíveis num determinado dispositivo FPGA (memória, unidades aritméticas, recursos lógicos) com o objetivo de maximizar o desempenho de aplicações selecionadas. Serão consideradas aplicações alvo no domínio do processamento de imagem e de "machine learning". Uma vez selecionada uma arquitetura base, a especialização para uma aplicação (ou classe de aplicações) terá por base a configuração de 3 componentes fundamentais: organização do sistema de memória distribuída (construído com os blocos de memória RAM internos da FPGA), organização das unidades de processamento aritmético (que podem ser heterogéneas) e dimensão dos caminhos de dados. O sistema a desenvolver deverá ser desenhado ao nível RTL, em Verilog, e contemplar um processo automatizado para personalizar o acelerador a partir de um conjunto de especificações definidas com base nas características da aplicação alvo. Esse processo de personalização poderá ser feito com base na definição de parâmetros em Verilog, ou também recorrendo a aplicações dedicadas, a desenvolver, para gerar diretamente código Verilog. Deverá também ser desenvolvido um conjunto elementar de ferramentas de suporte, nomeadamente para geração do código a executar pelo processador. Como validação final, pretende-se integrar e demonstrar o acelerador num sistema de processamento de imagem em tempo real

ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory

In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design

Anchoring digital maps as rough guides : a practice-orientated digital sociology of map use

This thesis provides a theoretical contribution towards understanding how, and to what extent, people’s engagements with digital maps feature in the constitution of their social practices. Existing theory tends not to focus on people as active interpreters that engage with digital maps across a variety of contexts, or on the influence of their map use on wider sets of social practices. Addressing this, the thesis draws on practice theory, media studies, and internet studies to develop a conceptual framework, applying it to empirical findings to address three research questions: (1) How do people engage with digital maps; (2) How do people engage with the web-based affordances of digital maps, such as those for collaboration, sharing, and end-user amendment/generation of content; and (3) What influence does people’s engagement with digital maps have on the way they perform wider sets of social practices? The research provides insights from three contexts, each operating at a different temporal scale: home choice covers longer-term processes of selecting and viewing properties before buying or renting; countryside leisure-walking covers mid-term processes of route-planning and assessment; University orientation covers shorter-term processes of navigation and gaining orientation around campus. Those insights are gathered through: a scoping survey (N=260) to identify relevant contexts; 32 semi-structured interviews to initiate data analysis; and 3 focus groups to gather participant feedback (member validation) on the emerging analysis. The approach to data analysis borrows heavily from constructivist grounded theory (albeit sensitised by practice theory ontology) to generate seven concepts. Together, the concepts constitute a practicetheory oriented digital sociology of map use. Overall, this thesis argues that digital maps are engaged with as mundane technologies that partially anchor people’s senses of place and security (physical and ontological), their performance of practices and social positions, and more broadly, the movement and distribution of bodies in space