Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Machine Learning for Run-Time Energy Optimisation in Many-Core Systems

In recent years, the focus of computing has moved away from performance-centric serial computation to energy-efficient parallel computation. This necessitates run-time optimisation techniques to address the dynamic resource requirements of different applications on many-core architectures. In this paper, we report on intelligent run-time algorithms which have been experimentally validated for managing energy and application performance in many-core embedded system. The algorithms are underpinned by a cross-layer system approach where the hardware, system software and application layers work together to optimise the energy-performance trade-off. Algorithm development is motivated by the biological process of how a human brain (acting as an agent) interacts with the external environment (system) changing their respective states over time. This leads to a pay-off for the action taken, and the agent eventually learns to take the optimal/best decisions in future. In particular, our online approach uses a model-free reinforcement learning algorithm that suitably selects the appropriate voltage-frequency scaling based on workload prediction to meet the applications’ performance requirements and achieve energy savings of up to 16% in comparison to state-of-the-art-techniques, when tested on four ARM A15 cores of an ODROID-XU3 platform

Learning transfer-based adaptive energy minimization in embedded systems

Embedded systems execute applications with different performance requirements. These applications exercise the hardware differently depending on the types of computation being carried out, generating varying workloads with time. We will demonstrate that energy minimization with such workload and performance variations within (intra) and across (inter) applications is particularly challenging. To address this challenge we propose an online energy minimization approach, capable of minimizing energy through adaptation to these variations. At the core of the approach is an initial learning through reinforcement learning algorithm that suitably selects the appropriate voltage/frequency scalings (VFS) based on workload predictions to meet the applications’ performance requirements. The adaptation is then facilitated and expedited through learning transfer, which uses the interaction between the system application, runtime and hardware layers to adjust the power control levers. The proposed approach is implemented as a power governor in Linux and validated on an ARM Cortex-A8 running different benchmark applications. We show that with intra- and inter-application variations, our proposed approach can effectively minimize energy consumption by up to 33% compared to existing approaches. Scaling the approach further to multi-core systems, we also show that it can minimize energy by up to 18% with 2X reduction in the learning time when compared with a recently reported approach

A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design

With the continually growing use of portable computing devices and increasingly complex software applications, there is a constant push for low power high speed circuitry to support this technology. Because of the high usage and large complex circuitry required to carry out arithmetic operations used in applications such as digital signal processing, there has been a great focus on increasing the efficiency of computer arithmetic circuitry. A key player in the realm of computer arithmetic is the digital multiplier and because of its size and power consumption, it has moved to the forefront of today\u27s research. A digital reconfigurable multiplier architecture will be introduced. Regulated by a 2-bit control signal, the multiplier is capable of double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this thesis is centered on a recursive multiplication algorithm, where a large multiplication is carried out using recursions of simpler submultiplier modules. Within each sub-multiplier module, instead of carry save adder arrays, 4:2 compressor rows are utilized for partial product reduction, which present greater efficiency, thus result in lower delay and power consumption of the whole multiplier. In addition, a study of various digital logic circuit styles are initially presented, and then three different designs of 4:2 compressor in Domino Logic are presented and simulation results confirm the property of proposed design in terms of delay, power consumption and operation frequenc

Block level voltage

Over the past years, state-of-art power optimization methods move towards higher abstraction levels that result in more efficient power savings. Among existing power optimization approaches, dynamic power management (DPM) is considered to be one of the most effective strategies. Depending on abstraction levels, DPM can be implemented in different formats but here we focus on scheduling that is more suitable for real-time system design use. This differs from the concurrent scheduling approaches that start from either the HLS (High-Level Synthesis) or RTS (Real-Time System) point of view, we propose a synergy solution of both approaches, namely block-level voltage/frequency scheduling (BLVFS). The presented block-level voltage/ frequency scheduling approach shows a generic solution for low power SoC (System on Chip) system design while the approaches which belong to the HLS and RTS categories have a strong dependency on the system functionalities. Consider a SoC as a combination of heterogeneous functional blocks, our approach provides efficient power savings by dynamically scheduling the scaling of voltage and frequency at the same time. Simulation results indicate that by using heuristic based strategies significant power savings can be achieved

Development of a Step Down DC-DC Converter for Power Grid Energy Harvesting

This work contains an analysis of multiple topologies of DC-DC voltage buck con verters. The main goal of this Thesis is to study and design a functioning Step Down converter for capacitive coupling devices used for energy harvesting from the power AC grid. In order to achieve this goal, multiple topologies and circuits of this type of converter are studied and analysed, so that the requirements for the intended application are met. Since the input is obtained from the AC power grid and the output is connected to a supercapacitor, this results in a large input voltage (over 150V) and a low output voltage (between 1V to 3V), therefore the converter requires a step down voltage conversion ratio of around 130. The DC-DC converter should also have a large input impedance (around 50Mohm) to maximize the energy transferred from the power grid. This mode of operation is not common for regular inductance based DC-DC converters, making this a challenging problem. Moreover, since the amount of energy available from the capacitive coupling is very small, it is also necessary to develop a controller circuit that is capable of created a clock with a very low duty cycle while dissipating less than 50uW.Este trabalho visa analisar várias tipologias de conversores de tensão DC-DC deno minados conversores Buck. O principal objectivo desta Tese é estudar e projectar um conversor DC-DC abaixador de tensão para sistemas de acopelamento electromagnético capacitivo utilizada em aplicações de Energy Harvesting a partir da rede AC. De forma a cumprir este objectivo, várias tipologias são estudadas ao longo deste trabalho, de forma a cumprir as especificações exigidas. Uma vez que o sinal de entrada é obtido a partir da rede AC, e que o output está ligado a um supercondensador, isto faz com que a tensão de entrada seja elevado (Acima dos 150V) e a tensão de saída seja baixa (entre 1V e 3V), como tal o conversor precisa de um rácio de abaixamento bastante elevado de cerca de 130 vezes. O conversor DC-DC deve também ter uma impedância de entrada elevada (cerca de 50MOhm) por forma a maximizar a energia transferida da rede de energia. Estas condições de funcionamento não são habituais para conversores DC-DC indutivos, o que torna este um problema muito desafiante. Adicionalmente, uma vez que a energia disponivel devido ao acopelamento capacitivo é muito reduzida, é necessário desenvolver um circuito controlador capaz gerar um sinal de relógio com um duty cycle reduzido enquanto dissipa menos de 50uW de potência

The Kiel Esterel processor: a multi-threaded reactive processor

Many embedded systems belong to the class of reactive systems, which continuously react to inputs from the environment by generating corresponding outputs. The programming of reactive systems typically requires the use of non-standard control flow constructs, such as concurrency or exception handling. Most programming languages do not support these constructs at all, or their use induces non-deterministic program behavior. To address these difficulties, the synchronous language Esterel has been developed to express reactive control flow patterns in a concise manner, with a clear semantics that imposes deterministic program behavior under all circumstances. There are different options to synthesize an Esterel program into a concrete system, e.g., software, hardware, and HW/SW co-design implementations. However, these classical synthesis approaches suffer from the limitations of traditional processors, with their instruction set architectures geared towards the sequential von-Neumann execution model, or they are very inflexible if HW synthesis is involved. Recently, another alternative for synthesizing Esterel has emerged, the reactive processing approach. Here the Esterel program is running on a processor that has been developed specifically for reactive systems. However, the main challenge when designing a reactive architecture is the handling of control. This thesis presents the Kiel Esterel Processor (KEP). In the KEP, the multi-threaded reactive architecture is responsible for managing the control flow of all threads. The KEP Instruction Set Architecture is complete in that it allows a direct mapping of all Esterel statements onto KEP assembler. It supports Esterel’s concurrency operator || in a very precise, direct and efficient way. It also supports full Esterel preemptions, i.e., the delayed and immediate strong/weak abortion and suspension. All other Esterel kernel statements, e.g., the Esterel exception, delay, and signal emission, etc., are also implemented directly and semantically accurate by the KEP. As the experimental comparison with a 32-bit commercial RISC processor indicates, the KEP has advantages in terms of memory use, execution speed, and energy consumption. Another advantage is the predictability of its timing behavior at the program level

Power Optimization and Management in Embedded Systems

Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance and quality of service (QoS). Power-aware high-level language compilers, dynamic power management policies, memory management schemes, bus encoding techniques, and hardware design tools are needed to meet these often-conflicting design requirements. This paper reviews techniques and tools for power-efficient embedded system design, considering the hardware platform, the application software, and the system software. Design examples from an Intel StrongARM based system are provided to illustrate the concepts and the techniques. This paper is not intended as a comprehensive review, rather as a starting point for understanding poweraware design methodologies and techniques targeted toward embedded systems