High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

A survey on scheduling and mapping techniques in 3D Network-on-chip

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions

Detector Technologies for CLIC

The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It is foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. It offers a rich physics program including direct searches as well as the probing of new physics through a broad set of precision measurements of Standard Model processes, particularly in the Higgs-boson and top-quark sectors. The precision required for such measurements and the specific conditions imposed by the beam dimensions and time structure put strict requirements on the detector design and technology. This includes low-mass vertexing and tracking systems with small cells, highly granular imaging calorimeters, as well as a precise hit-time resolution and power-pulsed operation for all subsystems. A conceptual design for the CLIC detector system was published in 2012. Since then, ambitious R&D programmes for silicon vertex and tracking detectors, as well as for calorimeters have been pursued within the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector requirements with innovative technologies. This report introduces the experimental environment and detector requirements at CLIC and reviews the current status and future plans for detector technology R&D.Comment: 152 pages, 116 figures; published as CERN Yellow Report Monograph Vol. 1/2019; corresponding editors: Dominik Dannheim, Katja Kr\"uger, Aharon Levy, Andreas N\"urnberg, Eva Sickin

A Digital Manufacturing Process For Three-Dimensional Electronics

Additive manufacturing (AM) offers the ability to produce devices with a degree of three-dimensional complexity and mass customisation previously unachievable with subtractive and formative approaches. These benefits have not transitioned into the production of commercial electronics that still rely on planar, template-driven manufacturing, which prevents them from being tailored to the end user or exploiting conformal circuitry for miniaturisation. Research into the AM fabrication of 3D electronics has been demonstrated; however, because of material restrictions, the durability and electrical conductivity of such devices was often limited. This thesis presents a novel manufacturing approach that hybridises the AM of polyetherimide (PEI) with chemical modification and selective light-based synthesis of silver nanoparticles to produce 3D electronic systems. The resulting nanoparticles act as a seed site for the electroless deposition of copper. The use of high-performance materials for both the conductive and dielectric elements created devices with the performance required for real-world applications. For printing PEI, a low-cost fused filament fabrication (FFF); also known as fused deposition modelling (FDM), printer with a unique inverted design was developed. The orientation of the printer traps hot air within a heated build environment that is open on its underside allowing the print head to deposit the polymer while keeping the sensitive components outside. The maximum achievable temperature was 120 °C and was found to reduce the degree of warping and the ultimate tensile strength of printed parts. The dimensional accuracy was, on average, within 0.05 mm of a benchmark printer and fine control over the layer thickness led to the discovery of flexible substrates that can be directly integrated into rigid parts. Chemical modification of the printed PEI was used to embed ionic silver into the polymer chain, sensitising it to patterning with a 405 nm laser. The rig used for patterning was a re-purposed vat-photopolymerisation printer that uses a galvanometer to guide the beam that is focused to a spot size of 155 µm at the focal plane. The positioning of the laser spot was controlled with an open-sourced version of the printers slicing software. The optimal laser patterning parameters were experimentally validated and a link between area-related energy density and the quality of the copper deposition was found. In tests where samples were exposed to more than 2.55 J/cm^2, degradation of the polymer was experienced which produced blistering and delamination of the copper. Less than 2.34 J/cm^2 also had negative effect and resulted in incomplete coverage of the patterned area. The minimum feature resolution produced by the patterning setup was 301 µm; however, tests with a photomask demonstrated features an order of magnitude smaller. The non-contact approach was also used to produce conformal patterns over sloped and curved surfaces. Characterisation of the copper deposits found an average thickness of 559 nm and a conductivity of 3.81 × 107 S/m. Tape peel and bend fatigue testing showed that the copper was ductile and adhered well to the PEI, with flexible electronic samples demonstrating over 50,000 cycles at a minimum bend radius of 6.59 mm without failure. Additionally, the PEI and copper combination was shown to survive a solder reflow with peak temperatures of 249°C. Using a robotic pick and place system a test board was automatically populated with surface mount components as small as 0201 resistors which were affixed using high-temperature, Type-V Tin-Silver-Copper solder paste. Finally, to prove the process a range of functional demonstrators were built and evaluated. These included a functional timer circuit, inductive wireless power coils compatible with two existing standards, a cylindrical RF antenna capable of operating at several frequencies below 10 GHz, flexible positional sensors, and multi-mode shape memory alloy actuators

Cherub: A hardware distributed single shared address space memory architecture

Increased computer throughput can be achieved through the use of parallel processing. The granularity of a parallel program is the average number of instructions performed by the tasks constituting it. Coarse-grained programs typically execute huge numbers of instructions per task (w 105). The tasks in fine-grained programs are typically short (æ 103). In general, the finer the program grain, the greater the potential for exploiting parallelism. Amdahl’s Law shows that in the absence of overheads, the more potential parallelism that is realised in an algorithm, the faster it will be. The economical granularity of tasks is determined by the intertask communications overhead. Break-even occurs when processing is approximately equally divided between useful work and overhead. The two common parallel programming paradigms are shared variable and message passing. Shared variable is, in general, the more natural of the two as it allows implicit communication between tasks. This encourages the programmer to make use of fine-grained tasks. The message passing paradigm requires explicit communication between tasks. This encourages the programmer to use coarser-grained tasks. Two kinds of parallel architecture have become established. The first is the multiprocessor, which is built around a shared bus giving broadcast communications and a shared memory. This is characterised by low communications overhead, but limited scalability. The second is the multicomputer, which is based on point-to-point communications with larger communications overhead, but good scalability. Quantitatively, the low overhead of the multiprocessor is well matched to fine-grain tasks and, hence, to supporting the shared variable paradigm, while the high overhead of the multicomputer matches it to coarse-grain parallelism and, hence, to the message passing paradigm. Currently, there appears to be no middle ground in parallel computing; an architecture which can support both several hundred medium-grained (« 104 instructions) parallel tasks and the shared variable programming paradigm would be advantageous in many applications. This thesis asserts that it is possible to implement a new computer architecture, Cherub, which has at least 200 processors and is able to support shared variable programming with an optimal task granularity of around 104 instructions. This can be achieved through the combination of a hardware-based distributed shared single address space and a wafer-scale communications network. To support the thesis, the dissertation first specifies a programmer’s interface to Cherub which is simple enough to implement in hardware. It then designs algorithms which provide this interface, allowing the requirements of the underlying network to be estimated. Finally, a wafer scale communications network is outlined, and simulations are used to demonstrate that it can provide the performance required to successfully implement Cherub

Microfabricated liquid density sensors using polyimide-guided surface acoustic waves

The simultaneous measurements of liquid density and refractive index on the same liquid sample are desirable. This thesis investigates the development of a micro- fabricated liquid density sensor that can be integrated into existing refractometers. A discussion of density sensing techniques and review of suitable sensors is given, leading to the choice of a Love mode surface acoustic wave (SAW) device. Love modes are formed by focussing the acoustic energy in a thin waveguide layer on a surface acoustic wave device. The horizontal-shear wave motion reduces attenuation in liquid environments, and the high surface energy density theoretically gives the highest sensitivity of all SAW devices. This study follows the development of a Love mode liquid density sensor using a polyimide waveguide layer. The novel use of polyimide offers simple and cheap fabrication, and theoretically gives a very high sensitivity to surface loading due to its low acoustic velocity. Love mode devices were fabricated with different polyimide waveguide thicknesses. The optimum thickness for a compromise between low loss and high sensitivity was 0.90 - 1.0 μm. These devices exhibited a linear shift in frequency with the liquid density-viscosity product for low viscosities. The response was smaller for high viscosities due to non-Newtonian liquid behaviour. Dual delay-line structures with a smooth 'reference' and corrugated 'sense' delay- lines were used to trap the liquid and separate the density from the density-viscosity product. A sensitivity up to 0.13 μgcm(^-3)Hz(^-1) was obtained. This is the highest density sensitivity obtained from an acoustic mode sensor. Experimental results show a zero temperature coefficient of frequency is possible using polyimide waveguides. These are the first Love mode devices that demonstrate temperature independence, highlighting the importance of polyimide as a new waveguide material

Primitives and design of the intelligent pixel multimedia communicator

Communication systems arc an ever more essential component of our modern global society. Mobile communications systems are still in a state of rapid advancement and growth. Technology is constantly evolving at a rapid pace in ever more diverse areas and the emerging mobile multimedia based communication systems offer new challenges for both current and future technologies. To realise the full potential of mobile multimedia communication systems there is a need to explore new options to solve some of the fundamental problems facing the technology. In particular, the complexity of such a system within an infrastructure framework that is inherently limited by its power sources and has very restricted transmission bandwidth demands new methodologies and approaches

Sincronização em sistemas integrados a alta velocidade

Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm