Power Management Circuits for Low-Power RF Energy Harvesters

The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Rectifying the output of vibrational piezoelectric energy harvester using quantum dots

Piezoelectric energy harvester scavenges mechanical vibrations and generates electricity. Researchers have strived to optimize the electromechanical structures and to design necessary external power management circuits, aiming to deliver high power and rectified outputs ready for serving as batteries. Complex deformation of the mechanical structure results in charges with opposite polarities appearing on same surface, leading to current loss in the attached metal electrode. External power management circuits such as rectifiers comprise diodes that consume power and have undesirable forward bias. To address the above issues, we devise a novel integrated piezoelectric energy harvesting device that is structured by stacking a layer of quantum dots (QDs) and a layer of piezoelectric material. We find that the QD can rectify electrical charges generated from the piezoelectric material because of its adaptable conductance to the electrochemical potentials of both sides of the QDs layer, so that electrical current causing energy loss on the same surface of the piezoelectric material can be minimized. The QDs layer has the potential to replace external rectification circuits providing a much more compact and less power-consumption solution

MOCAST 2021

The 10th International Conference on Modern Circuit and System Technologies on Electronics and Communications (MOCAST 2021) will take place in Thessaloniki, Greece, from July 5th to July 7th, 2021. The MOCAST technical program includes all aspects of circuit and system technologies, from modeling to design, verification, implementation, and application. This Special Issue presents extended versions of top-ranking papers in the conference. The topics of MOCAST include:Analog/RF and mixed signal circuits;Digital circuits and systems design;Nonlinear circuits and systems;Device and circuit modeling;High-performance embedded systems;Systems and applications;Sensors and systems;Machine learning and AI applications;Communication; Network systems;Power management;Imagers, MEMS, medical, and displays;Radiation front ends (nuclear and space application);Education in circuits, systems, and communications

Photovoltaic stand-alone modular systems, phase 2

The final hardware and system qualification phase of a two part stand-alone photovoltaic (PV) system development is covered. The final design incorporated modular, power blocks capable of expanding incrementally from 320 watts to twenty kilowatts (PK). The basic power unit (PU) was nominally rated 1.28 kWp. The controls units, power collection buses and main lugs, electrical protection subsystems, power switching, and load management circuits are housed in a common control enclosure. Photo-voltaic modules are electrically connected in a horizontal daisy-chain method via Amp Solarlok plugs mating with compatible connectors installed on the back side of each photovoltaic module. A pair of channel rails accommodate the mounting of the modules into a frameless panel support structure. Foundations are of a unique planter (tub-like) configuration to allow for world-wide deployment without restriction as to types of soil. One battery string capable of supplying approximately 240 ampere hours nominal of carryover power is specified for each basic power unit. Load prioritization and shedding circuits are included to protect critical loads and selectively shed and defer lower priority or noncritical power demands. The baseline system, operating at approximately 2 1/2 PUs (3.2 kW pk.) was installed and deployed. Qualification was successfully complete in March 1983; since that time, the demonstration system has logged approximately 3000 hours of continuous operation under load without major incident

Circuit design techniques for Power Efficient Microscale Energy Harvesting Systems

Power Management is considered one of the hot topics nowadays, as it is already known that all integrated circuits need a stable supply with low noise, a constant voltage level across time, and the ability to supply large range of loads. Normal batteries do not provide those specifications. A new concept of energy management called energy harvesting is introduced here. Energy harvesting means collecting power from ambient resources like solar power, Radio Frequency (RF) power, energy from motion...etc. The Energy is collected by means of a transducer that directly converts this energy into electrical energy that can be managed by design to supply different loads. Harvested energy management is critical because normal batteries have to be replaced with energy harvesting modules with power management, in order to make integrated circuits fully autonomous; this leads to a decrease in maintenance costs and increases the life time. This work covers the design of an energy harvesting system focusing on micro-scale solar energy harvesting with power management. The target application of this study is a Wireless Sensor Node/Network (WSN) because its applications are very wide and power management in it is a big issue, as it is very hard to replace the battery of a WSN after deployment. The contribution of this work is mainly shown on two different scopes. The first scope is to propose a new tracking technique and to verify on the system level. The second scope is to propose a new optimized architecture for switched capacitor based power converters. At last, some future recommendations are proposed for this work to be more robust and reliable so that it can be transfered to the production phase. The proposed system design is based on the sub-threshold operation. This design approach decreases the amount of power consumed in the control circuit. It can efficiently harvest the maximum power possible from the photo-voltaic cell and transfer this power to the super-capacitor side with high efficiency. It shows a better performance compared to the literature work. The proposed architecture of the charge pump is more efficient in terms of power capability and knee frequency over the basic linear charge pump topology. Comparison with recent topologies are discussed and shows the robustness of the proposed technique

Analysis and application of improved feedthrough logic

Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity

Power Management Circuits for Front-End ASICs Employed in High Energy Physics Applications

The instrumentation of radiation detectors for high energy physics calls for the development of very low-noise application-specific integrated-circuits and demanding system-level design strategies, with a particular focus on the minimisation of inter-ference noise from power anagement circuitry. On the other hand, the aggressive pixelisation of sensors and associated front-end electronics, and the high radiation exposure at the innermost tracking and vertex detectors, requires radiation-aware design and radiation-tolerant deep sub-micron CMOS technologies. This thesis explores circuit design techniques towards radiation tolerant power management integrated circuits, targeting applications on particle detectors and monitoring of accelerator-based experiments, aerospace and nuclear applications. It addresses advantages and caveats of commonly used radiation-hard layout techniques, which often employ Enclosed Layout or H-shaped transistors, in respect to the use of linear transistors. Radiation tolerant designs for bandgap circuits are discussed, and two different topologies were explored. A low quiescent current bandgap for sub-1 V CMOS circuits is proposed, where the use of diode-connected MOSFETs in weak-inversion is explored in order to increase its radiation tolerance. An any-load stable LDO architecture is proposed, and three versions of the design using different layout techniques were implemented and characterised. In addition, a switched DC-DC Buck converter is also studied. For reasons concerning testability and silicon area, the controller of the Buck converter is on-chip, while the inductance and the power transistors are left on-board. A prototype test chip with power management IP blocks was fabricated, using a TSMC 65 nm CMOS technology. The chip features Linear, ELT and H-shape LDO designs, bandgap circuits and a Buck DC-DC converter. We discuss the design, layout and test results of the prototype. The specifications in terms of voltage range and output current capability are based on the requirements set for the integrated on-detector electronics of the new CGEM-IT tracker for the BESIII detector. The thesis discusses the fundamental aspects of the proposed on-detector electronics and provides an in-depth depiction of the front-end design for the readout ASIC

Design considerations of sub-mW indoor light energy harvesting for wireless sensor systems

For most wireless sensor networks, one common and major bottleneck is the limited battery lifetime. The frequent maintenance efforts associated with battery replacement significantly increase the system operational and logistics cost. Unnoticed power failures on nodes will degrade the system reliability and may lead to system failure. In building management applications, to solve this problem, small energy sources such as indoor light energy are promising to provide long-term power to these distributed wireless sensor nodes. This paper provides comprehensive design considerations for an indoor light energy harvesting system for building management applications. Photovoltaic cells characteristics, energy storage units, power management circuit design and power consumption pattern of the target mote are presented. Maximum power point tracking circuits are proposed which significantly increase the power obtained from the solar cells. The novel fast charge circuit reduces the charging time. A prototype was then successfully built and tested in various indoor light conditions to discover the practical issues of the design. The evaluation results show that the proposed prototype increases the power harvested from the PV cells by 30% and also accelerates the charging rate by 34% in a typical indoor lighting condition. By entirely eliminating the rechargeable battery as energy storage, the proposed system would expect an operational lifetime 10-20 years instead of the current less than 6 months battery lifetim