Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.Ph.D.Committee Chair: Kohl, Paul A.; Committee Co-Chair: Allen, Sue Ann Bidstrup; Committee Member: Carter, W. Brent; Committee Member: Frazier, Albert B; Committee Member: Hess, Dennis; Committee Member: Meredith, Carso

Study of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnects

textThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.Physic

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Surface processing of nanoporous low dielectric constant thin films

Master'sMASTER OF SCIENC

Plasma Damage on Low-k Dielectric Materials

Low dielectric constant (low-k) materials as an interconnecting insulator in integrated circuits are essential for resistance-capacitance (RC) time delay reduction. Plasma technology is widely used for the fabrication of the interconnects, such as dielectric etching, resisting ashing or stripping, barrier metal deposition, and surface treatment. During these processes, low-k dielectric materials may be exposed to the plasma environments. The generated reactive species from the plasma react with the low-k dielectric materials. The reaction involves physical and chemical effects, causing degradations for low-k dielectric materials. This is called “plasma damage” on low-k dielectric materials. Therefore, this chapter is an attempt to provide an overview of plasma damage on the low-k dielectric materials

Cu Electrodeposition on Ru-Ta and Corrosion of Plasma Treated Cu in Post Etch Cleaning Solution

In this work, the possibility of Cu electrodeposition on Ru-Ta alloy thin films is explored. Ru and Ta were sputter deposited on Si substrate with different composition verified by RBS. Four point probe, XRD, TEM and AFM were used to study the properties of Ru-Ta thin films such as sheet resistance, crystallinity, grain size, etc. Cyclic voltammetry is used to study the Cu electrodeposition characteristics on Ru-Ta after various surface pretreatments. The results provide insights on the removal of Ta oxide such that it enables better Cu nucleation and adhesion. Bimetallic corrosion of Cu on modified Ru-Ta surface was studied in CMP related chemicals. In Cu interconnect fabrication process, the making of trenches and vias on low-k dielectric films involves the application of fluorocarbon plasma etch gases. Cu microdots deposited on Ru and Ta substrate were treated by fluorocarbon plasma etch gases such as CF4, CF4+O2, CH2F2, C4F8 and SF6 and investigated by using x-ray photoelectron spectroscopy, contact angle measurement and electrochemical techniques. Micropattern corrosion screening technique was used to measure the corrosion rate of plasma treated Cu. XPS results revealed different surface chemistry on Cu after treating with plasma etching. The fluorine/carbon ratio of the etching gases results in different extent of fluorocarbon polymer residues and affects the cleaning efficiency and Cu corrosion trends

Copper Diffusion Barrier Deposition on Integrated Circuit Devices by Atomic Layer Deposition Technique

Transfer from aluminum to copper metallization and decreasing feature size of integrated circuit devices generated a need for new diffusion barrier process. Copper metallization comprised entirely new process flow with new materials such as low-k insulators and etch stoppers, which made the diffusion barrier integration demanding. Atomic Layer Deposition technique was seen as one of the most promising techniques to deposit copper diffusion barrier for future devices. Atomic Layer Deposition technique was utilized to deposit titanium nitride, tungsten nitride, and tungsten nitride carbide diffusion barriers. Titanium nitride was deposited with a conventional process, and also with new in situ reduction process where titanium metal was used as a reducing agent. Tungsten nitride was deposited with a well-known process from tungsten hexafluoride and ammonia, but tungsten nitride carbide as a new material required a new process chemistry. In addition to material properties, the process integration for the copper metallization was studied making compatibility experiments on different surface materials. Based on these studies, titanium nitride and tungsten nitride processes were found to be incompatible with copper metal. However, tungsten nitride carbide film was compatible with copper and exhibited the most promising properties to be integrated for the copper metallization scheme. The process scale-up on 300 mm wafer comprised extensive film uniformity studies, which improved understanding of non-uniformity sources of the ALD growth and the process-specific requirements for the ALD reactor design. Based on these studies, it was discovered that the TiN process from titanium tetrachloride and ammonia required the reactor design of perpendicular flow for successful scale-up. The copper metallization scheme also includes process steps of the copper oxide reduction prior to the barrier deposition and the copper seed deposition prior to the copper metal deposition. Easy and simple copper oxide reduction process was developed, where the substrate was exposed gaseous reducing agent under vacuum and at elevated temperature. Because the reduction was observed efficient enough to reduce thick copper oxide film, the process was considered also as an alternative method to make the copper seed film via copper oxide reduction.Vuoden 2006 lopussa amerikkalainen mikroprosessorien valmistaja Intel aloitti kotitietokoneisiin suunnatun uuden sukupolven mikroprosessorin (CoreTM2 Duo, CoreTM2 quad-core and Xeon) valmistuksen. Tämän mahdollisti uusi prosessimenetelmä/materiaali, jota käytettiin transistorin pinnalla olevaan eristekalvoon, joka oli ainoastaan kymmenkunta atomikerrosta paksu. Kysymyksessä oli transistoritekniikan suurin muutos 1960-luvun jälkeen, mikä mahdollisti entistä pienemmän ja tehokkaamman mikroprosessorin valmistuksen. Vaikka uutinen vastaanotettiin myös Suomessa useissa tiedotusvälineissä, vain harva tiesi että kyseinen atomikerroskasvatusmenetelmä, ALD (= Atomic Layer Deposition), ja tuolla menetelmällä kasvatettu kalvo oli Suomessa kehitetty. Tämä olikin tiettävästi ensimmäinen kerta kun Suomessa kehitettyä teknologiaa käytettiin mikroprosessorien massatuotantoon. Väitöskirjatyössäni tutkitaan erästä toista prosessivaihetta mikroprosessorin valmistuksessa, jossa voitaisiin mahdollisesti käyttää ALD-menetelmää tulevaisuudessa. Olemme kehittäneet ALD-menetelmällä kasvatettavia materiaaleja, jotka soveltuvat diffuusionestokalvoiksi mikroprosessoriin. Diffuusionestokalvoa tarvitaan erottamaan johteet ja eristeet toisistaan mikroprosessorin sisäisessä johdotuksessa. Kalvon tehtävä on estää atomien kulkeutuminen kalvon toiselta puolelta toiselle puolelle. Työssämme on tutkittu erityisesti prosessien integrointiin liittyviä haasteita ja pyritty löytämään niihin ratkaisuja. Onnistuimme kehittämään uudeen ALD-prosessin, jonka avulla valmistimme hyvin sähköä johtavan materiaalin, wolframinitridikarbidin, joka oli myös erinomainen diffusionestomateriaali ja hyvin integroitavissa muihin mikroprosessorin valmistusvaiheisiin

Improvement of mechanical properties of mesoporous ultra low_k thin films after NH3 plasma treatment

Master'sMASTER OF SCIENC

Modeling and characterization of abrasive-free copper chemical mechanical planarization process

Master'sMASTER OF ENGINEERIN

Interaction between plasma and low-k dielectric materials

textWith the scaling of devices, integration of porous ultra low-κ dielectric materials into Cu interconnect becomes necessary. Low-k dielectric materials usually consist of a certain number of methyl groups and pores incorporated into a SiO₂ backbone structure to reduce the dielectric constant. They are frequently exposed to various plasmas, since plasma is widely used in VLSI semiconductor fabrication such as etching, ashing and deposition. This dissertation is aimed at exploring the interaction between plasma and low-κ dielectric surfaces. First, plasma assisted the atomic layer deposition (ALD) of Ta-based Cu barriers. Atomic layer deposition of Ta barriers is a self-limited surface reaction, determined by the function groups on the low-κ dielectric surface. But it was found TaCl₅ precursor could not nucleate on the organosilicate low-κ surface that was terminated with methyl groups. Radical NH[subscript x] beam, generated by a microwave plasma source, could activate the surface through exchanging with the methyl groups on the low-κ surface and providing active Si-NH[subscript x] nucleation sites for TaCl₅ precursors. Results from Monte Carlo simulation of the atomic layer deposition demonstrated that substrate chemistry was critical in controlling the film morphology. Second, the properties of low-κ dielectric materials tended to degrade under plasma exposure. In this dissertation, plasma damage of low-κ dielectric surface was investigated from a mechanistic point of view. Both carbon depletion and surface densification were observed on the top surface of damaged low-κ materials while the bulk remained largely uninfluenced. Plasma damage was found to be a complicated phenomenon involving both chemical and physical effects, depending on chemical reactivity and the energy and mass of the plasma species. With a downstream plasma source capable of separating ions from the plasma beam and an in-situ x-ray photoelectron spectroscopy (XPS) monitoring of the damage process, it was clear that ions played a more important role in the plasma damage process. Increase of dielectric constant after plasma damage was mainly attributed to moisture uptake and was confirmed with quantum chemistry calculation. Annealing was found to be effective in mitigating moisture uptake and thus restoring κ value. Finally, oxygen plasma damage to blanket and patterned low-κ dielectrics was studied in detail. Energetic ions in oxygen plasma contributed much to the loss of film hydrophobicity and dielectric constant through the formation of C=O and Si-OH. Based on results from residual gas analyses (RGA), three possible reaction paths leading to carbon depletion were proposed. This was followed by analytical solution of the evolution of carbon concentration during O₂ plasma damage. O₂ plasma damage to patterned CDO film was studied by TEM/EELS. And the damage behavior was simulated with Monte Carlo method. It was found that the charging potential distribution induced by plasma was important in determining the carbon loss in patterned low-k films. The charging potential distribution was mainly related to the geometry of low-k trench structures. To recover the dielectric constant, several recovery techniques were tried and briefly discussed.Physic