A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Implementation of Communication Receivers as Multi-Processor Software

Over the years, we have seen changes in the mobile communication systems starting from Advanced Mobile Phone System (AMPS) to 3G Universal Mobile Telecommunications System (UMTS) and now to 4G Long Term Evolution (LTE) advanced. Also the mobile terminals have more features to offer comparatively when it comes to supported applications for example Wireless Local Area Network (WLAN), Global-Positioning System (GPS) and high speed multimedia applications. As the mobile terminals are now evolving towards multistandard systems, the traditional approach of designing radio platforms has now been replaced by more flexible and cost-effective solutions. The challenge imposed by this multistandard approach in the implementation of mobile terminals is to integrate several radio technologies into a single device. Sharing components and processing resources between different radio technologies is the key in the implementation of multistandard terminals. Software implementation of the components is preferred because of shorter lead-time of software development and it also costs less to carry out necessary redesigns with software. In an effort to take up this challenge, the designers proposed Software Defined Radio (SDR) that allows multiple protocols to work on a System-on-Chip (SoC). The SDR implementations can follow either the Multi-Processor System-on-Chip (MPSoC) or the Coarse-Grain Reconfigurable Array (CGRA) paradigm. For this thesis work, a homogeneous MPSoC platform is used to accelerate the signal processing baseband algorithms of WCDMA and OFDM IEEE 802.11a WLAN standards. The performance comparison between single core and multi-core platforms has been made based on the number of clock cycles consumed. The idea is to exploit the inherent parallelism offered by homogeneous MPSoC platform and improve the execution times of computationally intensive algorithms like correlation operation and Fast Fourier Transform (FFT). The baseband signal processing components have been implemented in software and executed on an MPSoC platform to evaluate their performance. The multiprocessor platform has been used in an asymmetric manner in which each processing node has its own copy of application software and uses shared memory space for multiprocessor communication. Each of the processing nodes fetches and executes instructions from its own local instruction memory and is therefore independent from each other. Data Level Parallelism (DLP) has been exploited in the software implementation of the algorithms by performing identical operations simultaneously on different processors

Labeling Diversity for 2x2 WLAN Coded-Cooperative Networks

Labelling diversity is an efficient technique recently proposed in the literature and aims to improve the bit error rate(BER) performance of wireless local area network (WLAN) systems with two transmit and two receive antennas without increasing the transmit power and bandwidth requirements. In this paper, we employ labelling diversity with different space-time channel codes such as convolutional, turbo and low density parity check (LDPC) for both point-to-point and coded-cooperative communication scenarios. Joint iterative decoding schemes for distributed turbo and LDPC codes are also presented. BER performance bounds at an error floor (EF) region are derived and verified with the help of numerical simulations for both cooperative and non-cooperative schemes. Numerical simulations show that the coded-cooperative schemes with labelling diversity achieve better BER performances and use of labelling diversity at the source node significantly lowers relay outage probability and hence the overall BER performance of the coded-cooperative scheme is improved manifolds

Distributed Digital Radios for Land Mobile Radio Applications

The main objective of this dissertation is to develop the second generation of Distributed Digital Radio (DDR) technology. A DDR II modem provides an integrated voice/data service platform, higher data rates and better throughput performance as compared to a DDR I modem. In order to improve the physical layer performance of DDR modems an analytical framework is first developed to model the Bit Error Rate (BER) performance of Orthogonal Frequency Division Multiplexing over Frequency Modulation (OFDM/FM) systems. The use of OFDM provides a spectrally efficient method of transmitting data over LMR channels. However, the high Peak-to-Average (PAR) of OFDM signals results in either a low Signal-to-Noise Ratio (SNR) at FM receiver or a high non-linear distortion of baseband signal in the FM transmitter. This dissertation presents an analytical framework to highlight the impact of high PAR of OFDM signal on OFDM/FM systems. A novel technique for reduction of PAR of OFDM called Linear Scaling Technique (LST) is developed. The use of LST mitigates the signal distortion occurring in OFDM over FM systems. Another important factor which affects the throughput of LMR networks is the Push-to-Talk (PTT) delay. A PTT delay refers to the delay between the instant when a PTT switch on a conventional LMR radio is keyed/unkeyed and a response is observed at the radio output. It can be separated into a Receive-To-Transmit Switch Interval (RTSI) or a Transmit-To-Receive Switch Interval (TRSI). This dissertation presents the typical RTSI delay values, distributions and their impact on throughput performance of LMR networks. An analytical model is developed to highlight the asymmetric throughput problem and the unintentional denial of service (UDOS) occurring in heterogeneous LMR networks consisting of radios with different PTT delay profiles. This information will be useful in performance and capacity planning of LMR networks in future

Radio Communications

In the last decades the restless evolution of information and communication technologies (ICT) brought to a deep transformation of our habits. The growth of the Internet and the advances in hardware and software implementations modified our way to communicate and to share information. In this book, an overview of the major issues faced today by researchers in the field of radio communications is given through 35 high quality chapters written by specialists working in universities and research centers all over the world. Various aspects will be deeply discussed: channel modeling, beamforming, multiple antennas, cooperative networks, opportunistic scheduling, advanced admission control, handover management, systems performance assessment, routing issues in mobility conditions, localization, web security. Advanced techniques for the radio resource management will be discussed both in single and multiple radio technologies; either in infrastructure, mesh or ad hoc networks

Design and implementation of adaptive baseband predistorter for OFDM nonlinear transmitter. Simulation and measurement of OFDM transmitter in presence of RF high power amplifier nonlinear distortion and the development of adaptive digital predistorters based on Hammerstein approach.

The objective of this research work is to investigate, design and measurement of a digital predistortion linearizer that is able to compensate the dynamic nonlinear distortion of a High Power Amplifier (PA). The effectiveness of the proposed baseband predistorter (PD) on the performance of a WLAN OFDM transmitter utilizing a nonlinear PA with memory effect is observed and discussed. For this purpose, a 10W Class-A/B power amplifier with a gain of 22 dB, operated over the 3.5 GHz frequency band was designed and implemented. The proposed baseband PD is independent of the operating RF frequency and can be used in multiband applications. Its operation is based on the Hammerstein system, taking into account PA memory effect compensation, and demonstrates a noticeable improvement compared to memoryless predistorters. Different types of modelling procedures and linearizers were introduced and investigated, in which accurate behavioural models of Radio Frequency (RF) PAs exhibiting linear and nonlinear memory effects were presented and considered, based on the Wiener approach employing a linear parametric estimation technique. Three new linear methods of parameter estimation were investigated, with the aim of reducing the complexity of the required filtering process in linear memory compensation. Moreover, an improved wiener model is represented to include the nonlinear memory effect in the system. The validity of the PA modelling approaches and predistortion techniques for compensation of nonlinearities of a PA were verified by several tests and measurements. The approaches presented, based on the Wiener system, have the capacity to deal with the existing trade-off between accuracy and convergence speed compared to more computationally complex behavioural modelling algorithms considering memory effects, such as those based on Volterra series and Neural Networks. In addition, nonlinear and linear crosstalks introduced by the power amplifier nonlinear behaviour and antennas mutual coupling due to the compact size of a MIMO OFDM transmitter have been investigated