Electrical and Electronic Engineering, Imperial College London
Doi
Abstract
Linear power amplifiers used to implement the Ultra-Wideband standard must be
backed off from optimum power efficiency to meet the standard specifications and
the power efficiency suffers. The problem of low efficiency can be mitigated by polar
modulation. Digital polar architectures have been employed on numerous wireless
standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved
are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm.
Can the architecture be employed on wireless standards with low-power and high
fractional bandwidth requirements and yet achieve good power efficiency?
To answer these question, this thesis studies the application of a digital polar transmitter
architecture with parallel amplifier stages for UWB. The concept of the digital
transmitter is motivated and inspired by three factors. First, unrelenting advances
in the CMOS technology in deep-submicron process and the prevalence of low-cost
Digital Signal processing have resulted in the realization of higher level of integration
using digitally intensive approaches. Furthermore, the architecture is an evolution
of polar modulation, which is known for high power efficiency in other wireless applications.
Finally, the architecture is operated as a digital-to-analog converter which
circumvents the use of converters in conventional transmitters.
Modeling and simulation of the system architecture is performed on the Agilent Advanced
Design System Ptolemy simulation platform. First, by studying the envelope
signal, we found that envelope clipping results in a reduction in the peak-to-average
power ratio which in turn improves the error vector magnitude performance (figure
of merit for the study). In addition, we have demonstrated that a resolution of three
bits suffices for the digital polar transmitter when envelope clipping is performed.
Next, this thesis covers a theoretical derivation for the estimate of the error vector
magnitude based on the resolution, quantization and phase noise errors. An analysis
on the process variations - which result in gain and delay mismatches - for a
digital transmitter architecture with four bits ensues. The above studies allow RF
designers to estimate the number of bits required and the amount of distortion that
can be tolerated in the system.
Next, a study on the circuit implementation was conducted. A DPA that comprises
7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7
cascode transistors (individually connected in series with the bottom amplifiers)
digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB
signal at the output. Through the use of NFET models from the IBM 130-nm
technology, our simulation reveals that our DPA is able to achieve an EVM of -
22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency
with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth
of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering
-1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power.
In addition, we performed a yield analysis on the digital polar amplifier, based
on unit-weighted and binary-weighted architecture, when gain variations are introduced
in all the individual stages. The dynamic element matching method is also
introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations
reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a
standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%,
while the yields of the unit-weighted architectures are in the neighbourhood of 95%.
Moreover, the dynamic element matching technique demonstrates an improvement
in the yield by approximately 3%.
Finally, a hardware implementation for this architecture based on software-defined
arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar
transmitter under ideal combining conditions fulfill the European Computer Manufacturers
Association requirements. The proposed experimental setup, believed to
be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture
for Ultra-Wideband. In addition, we propose a number of power combining
techniques suitable for the hardware implementation. Spatial power combining, in
particular, shows a high potential for the digital polar transmitter architecture.
The above studies demonstrate the feasibility of the digital polar architecture with
good power efficiency for a wideband wireless standard with low-power and high
fractional bandwidth requirements