Language applications for UEFI BIOS

textThe Unified Extensible Firmware Interface (UEFI) is the industry-standard Basic Input/Output System (BIOS) firmware specification used by modern desktop, portable, and server computers, and is increasingly being ported to today's new mobile form factors as well. UEFI is firmware responsible for bootstrapping the hardware, turning control over to an operating system loader, and then providing runtime services to the operating system. ANTLR (ANother Tool for Language Recognition) is a lexer-parser generator for reading, processing, executing, and translating structured text and binary files. It supersedes older technologies such as lex/yacc or flex/bison and is widely used to build languages and programming tools. ANTLR accepts a provided grammar and generates a parser that can build and walk parse trees. This report studies UEFI BIOS and compiler theory and demonstrates ways compiler theory can be leveraged to solve problems in the UEFI BIOS domain. Specifically, this report uses ANTLR to implement two language applications aimed at furthering the development of UEFI BIOS implementations. They are: 1. A software complexity analysis application for UEFI created that leverages ANTLR's standard general-purpose C language grammar. The complexity analysis application uses general-purpose and domain-specific measures to give a complexity score to UEFI BIOS modules. 2. An ANTLR grammar created for the VFR domain-specific language, and a sample application which puts the grammar to use. VFR is a language describing visual elements on a display; the sample application creates an HTML preview of VFR code without requiring a developer to build and flash a BIOS image on a target machine to see its graphical layout.Electrical and Computer Engineerin

Integer linear programming vs. graph-based methods in code generation

A common characterictic of many applications is that they are aimed at the high-volume consumer market, which is extremely cost-sensitive. However many of them impose stringent performance demands on the underlying system. Therefore the code generation must take into account the restrictions and features given by the target architecture while satisfying these performance demands. High-level language compilers often are unable to generate code meeting these requirements. One reason is the phase coupling problem between instruction scheduling and register allocation. Many compilers perform these tasks separately with each phase ignorant of the require- ments of the other. Commonly, each task is accomplished by using heuristic methods. As the goals of the two phases often conflict, whichever phase is performed first imposes constraints on the other, sometimes producing inefficient code. Integer linear programming (ILP) provides an integrated approach to the combined instruction scheduling and register allocation problem. This way, optimal solutions can be found - albeit at the cost of high compilation times. In our experiments, we considered as target processor the 32-bit DSP ADSP-2106x. We have examined two different ILP formulations and compared them with conventional approaches including list scheduling and the critical path method. Moreover, we have investigated approximations based on the ILP formulations; this way, compilation time can be reduced considerably while still producing near-optimal results. From the results of our implementation, we have concluded that integrating ILP formulations in conventional global algorithms is a promising method for generating high-quality code

Static resource models for code generation of embedded processors

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Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

A Modular Approach to Adaptive Reactive Streaming Systems

The latest generations of FPGA devices offer large resource counts that provide the headroom to implement large-scale and complex systems. However, there are increasing challenges for the designer, not just because of pure size and complexity, but also in harnessing effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules from diverse sources to promote modular design and reuse. Further, the capability to perform dynamic partial reconfiguration (DPR) of FPGA devices means that implemented systems can be made reconfigurable, allowing components to be changed during operation. However, use of DPR typically requires low-level planning of the system implementation, adding to the design challenge. This dissertation presents ReShape: a high-level approach for designing systems by interconnecting modules, which gives a ‘plug and play’ look and feel to the designer, is supported by tools that carry out implementation and verification functions, and is carried through to support system reconfiguration during operation. The emphasis is on the inter-module connections and abstracting the communication patterns that are typical between modules – for example, the streaming of data that is common in many FPGA-based systems, or the reading and writing of data to and from memory modules. ShapeUp is also presented as the static precursor to ReShape. In both, the details of wiring and signaling are hidden from view, via metadata associated with individual modules. ReShape allows system reconfiguration at the module level, by supporting type checking of replacement modules and by managing the overall system implementation, via metadata associated with its FPGA floorplan. The methodology and tools have been implemented in a prototype for a broad domain-specific setting – networking systems – and have been validated on real telecommunications design projects

International Aerospace and Ground Conference on Lightning and Static Electricity. 1984 technical papers. Supplement

The indirect effects of lightning on digital systems, ground system protection, and the corrosion properties of conductive materials are addressed. The responses of a UH-60A helicopter and tactical shelters to lightning and nuclear electromagnetic pulses are discussed

A Survey on Compiler Autotuning using Machine Learning

Since the mid-1990s, researchers have been trying to use machine-learning based approaches to solve a number of different compiler optimization problems. These techniques primarily enhance the quality of the obtained results and, more importantly, make it feasible to tackle two main compiler optimization problems: optimization selection (choosing which optimizations to apply) and phase-ordering (choosing the order of applying optimizations). The compiler optimization space continues to grow due to the advancement of applications, increasing number of compiler optimizations, and new target architectures. Generic optimization passes in compilers cannot fully leverage newly introduced optimizations and, therefore, cannot keep up with the pace of increasing options. This survey summarizes and classifies the recent advances in using machine learning for the compiler optimization field, particularly on the two major problems of (1) selecting the best optimizations and (2) the phase-ordering of optimizations. The survey highlights the approaches taken so far, the obtained results, the fine-grain classification among different approaches and finally, the influential papers of the field.Comment: version 5.0 (updated on September 2018)- Preprint Version For our Accepted Journal @ ACM CSUR 2018 (42 pages) - This survey will be updated quarterly here (Send me your new published papers to be added in the subsequent version) History: Received November 2016; Revised August 2017; Revised February 2018; Accepted March 2018

Design and development of an embedded flash memory integrated simulator for the automotive microcontroller firmware validation

Applicazioni automotive possono compromettere la sicurezza delle persone pertanto i componenti devono essere affidabili in qualsiasi condizione operativa. L'affidabilità può essere raggiunta testando i dispositivi dopo la produzione, progettare il test è un compito delicato in quanto non sono presenti fisicamente i primi prototipi del dispositivo. Realizziamo un simulatore di memorie flash integrate di un microcontrollore automotive per facilitare la progettazione dei tes