Performance-effective operation below Vcc-min

Continuous circuit miniaturization and increased process variability point to a future with diminishing returns from dynamic voltage scaling. Operation below Vcc-min has been proposed recently as a mean to reverse this trend. The goal of this paper is to minimize the performance loss due to reduced cache capacity when operating below Vcc-min. A simple method is proposed: disable faulty blocks at low voltage. The method is based on observations regarding the distributions of faults in an array according to probability theory. The key lesson, from the probability analysis, is that as the number of uniformly distributed random faulty cells in an array increases the faults increasingly occur in already faulty blocks. The probability analysis is also shown to be useful for obtaining insight about the reliability implications of other cache techniques. For one configuration used in this paper, block disabling is shown to have on the average 6.6% and up to 29% better performance than a previously proposed scheme for low voltage cache operation. Furthermore, block-disabling is simple and less costly to implement and does not degrade performance at or above Vcc-min operation. Finally, it is shown that a victim-cache enables higher and more deterministic performance for a block-disabled cache

Urine sampling and collection system

This specification defines the performance and design requirements for the urine sampling and collection system engineering model and establishes requirements for its design, development, and test. The model shall provide conceptual verification of a system applicable to manned space flight which will automatically provide for collection, volume sensing, and sampling of urine

Two-stage optimization method for efficient power converter design including light load operation

Power converter efficiency is always a hot topic for switch mode power supplies. Nowadays, high efficiency is required over a wide load range, e.g., 20%, 50% and 100% load. Computer-aided design optimization is developed in this research work, to optimize off-line power converter efficiency from light load to full load. A two-stage optimization method to optimize power converter efficiency from light load to full load is proposed. The optimization procedure first breaks the converter design variables into many switching frequency loops. In each fixed switching frequency loop, the optimal designs for 20%, 50% and 100% load are derived separately in the first stage, and an objective function using the optimization results in the first stage is formed in the second stage to consider optimizing efficiency at 20%, 50% and 100% load. Component efficiency models are also established to serve as the objective functions of optimizations. Prototypes 400V to 12V/25A 300W two-FET forward converters are built to verify the optimization results

Development of a microelectronic module Final report

Feasibility of operating gallium arsenide devices in high temperature microelectronic circuit

Development of an image converter of radical design

A long term investigation of thin film sensors, monolithic photo-field effect transistors, and epitaxially diffused phototransistors and photodiodes to meet requirements to produce acceptable all solid state, electronically scanned imaging system, led to the production of an advanced engineering model camera which employs a 200,000 element phototransistor array (organized in a matrix of 400 rows by 500 columns) to secure resolution comparable to commercial television. The full investigation is described for the period July 1962 through July 1972, and covers the following broad topics in detail: (1) sensor monoliths; (2) fabrication technology; (3) functional theory; (4) system methodology; and (5) deployment profile. A summary of the work and conclusions are given, along with extensive schematic diagrams of the final solid state imaging system product

Electromagnetic radiation screening of microcircuits for long life applications

The utility of X-rays as a stimulus for screening high reliability semiconductor microcircuits was studied. The theory of the interaction of X-rays with semiconductor materials and devices was considered. Experimental measurements of photovoltages, photocurrents, and effects on specified parameters were made on discrete devices and on microcircuits. The test specimens included discrete devices with certain types of identified flaws and symptoms of flaws, and microcircuits exhibiting deviant electrical behavior. With a necessarily limited sample of test specimens, no useful correlation could be found between the X-ray-induced electrical response and the known or suspected presence of flaws

B.O.G.G.L.E.S.: Boundary Optical GeoGraphic Lidar Environment System

The purpose of this paper is to describe a pseudo X-ray vision system that pairs a Lidar scanner with a visualization device. The system as a whole is referred to as B.O.G.G.L.E.S. There are several key factors that went into the development of this system and the background information and design approach are thoroughly described. B.O.G.G.L.E.S functionality is depicted through the use of design constraints and the analysis of test results. Additionally, many possible developments for B.O.G.G.L.E.S are proposed in the paper. This indicates that there are various avenues of improvement for this project that could be implemented in the future

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications