Schedulability analysis for systems with data and control dependencies

In this paper we present an approach to schedulability analysis for hard real-time systems with control and data dependencies. We consider distributed architectures consisting of multiple programmable processors, and the scheduling policy is based on a static priority preemptive strategy. Our model of the system captures both data and control dependencies, and the schedulability approach is able to reduce the pessimism of the analysis by using the knowledge about control and data dependencies. Extensive experiments as well as a real life example demonstrate the efficiency of our approach. 1

Influence of different abstractions on the performance analysis of distributed hard real-time systems

System level performance analysis plays a fundamental role in the design process of hard real-time embedded systems. Several different approaches have been presented so far to address the problem of accurate performance analysis of distributed embedded systems in early design stages. The existing formal analysis methods are based on essentially different concepts of abstraction. However, the influence of these different models on the accuracy of the system analysis is widely unknown, as a direct comparison of performance analysis methods has not been considered so far. We define a set of benchmarks aimed at the evaluation of performance analysis techniques for distributed systems. We apply different analysis methods to the benchmarks and compare the results obtained in terms of accuracy and analysis times, highlighting the specific effects of the various abstractions. We also point out several pitfalls for the analysis accuracy of single approaches and investigate the reasons for pessimistic performance prediction

Temporal Analysis of Static Priority Preemptive Scheduled Cyclic Streaming Applications using CSDF Models

Real-time streaming applications with cyclic data dependencies that are executed on multiprocessor systems with processor sharing usually require a temporal analysis to give guarantees on their temporal behavior at design time. Current accurate analysis techniques for cyclic applications that are scheduled with Static Priority Preemptive (SPP) schedulers are however limited to the analysis of applications that can be expressed with Homogeneous Synchronous Dataflow (HSDF) models, i.e. in which all tasks operate at a single rate. Moreover, it is required that both input and output buffers synchronize atomically at the beginnings and finishes of task executions, which is difficult to realize on many existing hardware platforms.\ud \ud This paper presents a temporal analysis approach for cyclic real-time streaming applications executed on multiprocessor systems with processor sharing and SPP scheduling that can be expressed using Cyclo-Static Dataflow (CSDF) models. This allows to model tasks with multiple phases and changing rates and furthermore resolves the problematic restriction that buffer synchronization must occur atomically at the boundaries of task executions. For that purpose a joint interference characterization over multiple phases is introduced, which realizes a significant accuracy improvement compared to an isolated consideration of interference.\ud \ud Applicability, efficiency and accuracy of the presented approach are evaluated in a case study using a WLAN 802.11p transceiver application. Thereby different use-cases of CSDF modeling are discussed, including a CSDF model relaxing the requirement of atomic synchronization

Algorithms for processors pipeline synthesis of embedded systems : cost, number of processors and latency minimization

Orientador: Alice Maria B. H. TokarniaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Este trabalho descreve três algoritmos para a síntese de sistemas embutidos atendendo à restrição de desempenho representada pela taxa de chegada dos dados, através de uma estrutura de pipeline de processadores para execução das tarefas, ao mesmo tempo em que minimizam diferentes parâmetros de qualidade dos sistemas: número de processadores; custo e latência total. Os algoritmos realizam o particionamento hardware-software das tarefas, a alocação dos processadores, o mapeamento e escalonamento das tarefas. A alocação de processadores e o mapeamento e escalonamento de tarefas são problemas classificados como NP-Completo e, portanto, foram aplicados métodos heurísticos para suas resoluções. Como exemplos de aplicação são apresentados os pipelines sintetizados pelos algoritmos para grafos sintéticos e para um compressor de áudio digital (AC3). Os pipelines sintetizados atingem métricas de qualidade superiores a outros algoritmos publicadosAbstract: This work presents three heuristics for sinthesizing pipelined embedded systems that satisfy a throughput constraint derived from the maximum input data are adopting a pipeline structure of processors while minimizing system quality parameters: cost, number of processors, or number of stages. The algorithms perform tasks hardware-software partitioning, processors allocation and task mapping and scheduling. Since processors allocation and task mapping and scheduling are NP-Complete problems, heuristics methods were applied. The examples present the pipelines synthesized by the algorithms for large synthetic systems comparing the quality parameters minimization results and for a real audio compressor (AC3) application. The pipelines reached quality metrics higher than other published algorithmsMestradoEngenharia de ComputaçãoMestre em Engenharia Elétric

Scheduling and Communication Synthesis for Distributed Real-Time Systems

EMBEDDED SYSTEMS ARE now omnipresent: from cellular phones to pagers, from microwave ovens to PDAs, almost all the devices we use are controlled by embedded systems. Many embedded systems have to fulfill strict requirements in terms of performance and cost efficiency. Emerging designs are usually based on heterogeneous architectures that integrate multiple programmable processors and dedicated hardware components. New tools which extend design automation to system level have to support the integrated design of both the hardware and software components of such systems. This thesis concentrates on aspects of scheduling and communication for embedded real-time systems. Special emphasis has been placed on the impact of the communication infrastructure and protocol on the overall system performance. The scheduling and communication strategies proposed are based on an abstract graph representation which captures, at process level, both the dataflow and the flow of control. We have considere..

SECURE REAL-TIME SMART GRID COMMUNICATIONS: A MICROGRID PERSPECTIVE

Microgrids are a key component in the evolution of the power grid. Microgrids are required to operate in both grid connected and standalone island mode using local sources of power. A major challenge in implementing microgrids is the communications and control to support transition from grid connected mode and operation in island mode. In this dissertation we propose a distributed control architecture to govern the operation of a microgrid. The func- tional communication requirements of primary, secondary and tertiary microgrid controls are considered. Communication technology media and protocols are laid out and a worst-case availability and latency analysis is provided. Cyber Security challenges to microgrids are ex- amined and we propose a secure communication architecture to support microgrid operation and control. A security model, including network, data, and attack models, is defined and a security protocol to address the real-time communication needs of microgrids is proposed. We propose a novel security protocol that is custom tailored to meet those challenges. The chosen solution is discussed in the context of other security options available in the liter- ature. We build and develop a microgrid co-simulation model of both the power system and communication networks, that is used to simulate the two fundamental microgrid power transition functions - transition from island to grid connected mode, and grid connected to island mode. The proposed distributed control and security architectures are analyzed in terms of performance. We further characterize the response of the power and communication subsystems in emergency situations: forced islanding and forced grid modes. Based on our findings, we generalize the results to the smart grid

Design and Power Management of an Offshore Medium Voltage DC Microgrid Realized Through High Voltage Power Electronics Technologies and Control

The growth in the electric power industry’s portfolio of Direct Current (DC) based generation and loads have captured the attention of many leading research institutions. Opportunities for using DC based systems have been explored in electric ship design and have been a proven, reliable solution for transmitting bulk power onshore and offshore. To integrate many of the renewable resources into our existing AC grid, a number of power conversions through power electronics are required to condition the equipment for direct connection. Within the power conversion stages, there is always a requirement to convert to or from DC. The AC microgrid is a conceptual solution proposed for integrating various types of renewable generation resources. The fundamental microgrid requirements include the capability of operating in islanding mode and/or grid connected modes. The technical challenges associated with microgrids include (1) operation modes and transitions that comply with IEEE1547 without extensive custom engineering and (2) control architecture and communication. The Medium Voltage DC (MVDC) architecture, explored by the University of Pittsburgh, can be visualized as a special type of DC microgrid. This dissertation is multi-faceted, focused on many design aspects of an offshore DC microgrid. The focal points of the discussion are focused on optimized high power, high frequency magnetic material performance in electric machines, transformers, and DC/DC power converters – all components found within offshore power system architectures. A new controller design based upon model reference control is proposed and shown to stabilize the electric motor drives (modeled as constant power loads), which serve as the largest power consuming entities in the microgrid. The design and simulation of a state-of-the-art multilevel converter for High Voltage DC (HVDC) is discussed and a component sensitivity analysis on fault current peaks is explored. A power management routine is proposed and evaluated as the DC microgrid is disturbed through various mode transitions. Finally, two communication protocols are described for the microgrid – one to minimize communication overhead inside the microgrid, and another to provide robust and scalable intra-grid communication. The work presented is supported by Asea Brown Boveri (ABB) Corporate Research Center within the Active Grid Infrastructure program, the Advanced Research Project Agency – Energy (ARPA-E) through the Solar ADEPT program, and Mitsubishi Electric Corporation (MELCO)

Predicting software performance in symmetric multi-core and multiprocessor Environments

With today\u27s rise of multi-core processors, concurrency becomes a ubiquitous challenge in software development.Performance prediction methods have to reflect the influence of multiprocessing environments on software performance in order to help software architects to find potential performance problems during early development phases. In this thesis, we address the influence of the operating system scheduler on software performance in symmetric multiprocessing environments