581 research outputs found

    Slocalization: Sub-{\mu}W Ultra Wideband Backscatter Localization

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    Ultra wideband technology has shown great promise for providing high-quality location estimation, even in complex indoor multipath environments, but existing ultra wideband systems require tens to hundreds of milliwatts during operation. Backscatter communication has demonstrated the viability of astonishingly low-power tags, but has thus far been restricted to narrowband systems with low localization resolution. The challenge to combining these complimentary technologies is that they share a compounding limitation, constrained transmit power. Regulations limit ultra wideband transmissions to just -41.3 dBm/MHz, and a backscatter device can only reflect the power it receives. The solution is long-term integration of this limited power, lifting the initially imperceptible signal out of the noise. This integration only works while the target is stationary. However, stationary describes the vast majority of objects, especially lost ones. With this insight, we design Slocalization, a sub-microwatt, decimeter-accurate localization system that opens a new tradeoff space in localization systems and realizes an energy, size, and cost point that invites the localization of every thing. To evaluate this concept, we implement an energy-harvesting Slocalization tag and find that Slocalization can recover ultra wideband backscatter in under fifteen minutes across thirty meters of space and localize tags with a mean 3D Euclidean error of only 30 cm.Comment: Published at the 17th ACM/IEEE Conference on Information Processing in Sensor Networks (IPSN'18

    High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

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    The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

    Autonomous smart antenna systems for future mobile devices

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    Along with the current trend of wireless technology innovation, wideband, compact size, low-profile, lightweight and multiple functional antenna and array designs are becoming more attractive in many applications. Conventional wireless systems utilise omni-directional or sectored antenna systems. The disadvantage of such antenna systems is that the electromagnetic energy, required by a particular user located in a certain direction, is radiated unnecessarily in every direction within the entire cell, hence causing interference to other users in the system. In order to limit this source of interference and direct the energy to the desired user, smart antenna systems have been investigated and developed. This thesis presents the design, simulation, fabrication and full implementation of a novel smart antenna system for future mobile applications. The design and characterisation of a novel antenna structure and four-element liner array geometry for smart antenna systems are proposed in the first stage of this study. Firstly, a miniaturised microstrip-fed planar monopole antenna with Archimedean spiral slots to cover WiFi/Bluetooth and LTE mobile applications has been demonstrated. The fundamental structure of the proposed antenna element is a circular patch, which operates in high frequency range, for the purpose of miniaturising the circuit dimension. In order to achieve a multi-band performance, Archimedean spiral slots, acting as resonance paths, have been etched on the circular patch antenna. Different shapes of Archimedean spiral slots have been investigated and compared. The miniaturised and optimised antenna achieves a bandwidth of 2.2GHz to 2.9GHz covering WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile standards. Then a four-element linear antenna array geometry utilising the planar monopole elements with Archimedean spiral slots has been described. All the relevant parameters have been studied and evaluated. Different phase shifts are excited for the array elements, and the main beam scanning range has been simulated and analysed. The second stage of the study presents several feeding network structures, which control the amplitude and phase excitations of the smart antenna elements. Research begins with the basic Wilkinson power divider configuration. Then this thesis presents a compact feeding network for circular antenna array, reconfigurable feeding networks for tuning the operating frequency and polarisations, a feeding network on high resistivity silicon (HRS), and an ultrawide-band (UWB) feeding network covering from 0.5GHz to 10GHz. The UWB feeding network is used to establish the smart antenna array system. Different topologies of phase shifters are discussed in the third stage, including ferrite phase shifters and planar phase shifters using switched delay line and loaded transmission line technologies. Diodes, FETs, MMIC and MEMS are integrated into different configurations. Based on the comparison, a low loss and high accurate Hittite MMIC analogue phase shifter has been selected and fully evaluated for this implementation. For the purpose of impedance matching and field matching, compact and ultra wideband CPW-to-Microstrip transitions are utilised between the phase shifters, feeding network and antenna elements. Finally, the fully integrated smart antenna array achieves a 10dB reflection coefficient from 2.25GHz to 2.8GHz, which covers WiFi/Bluetooth (2.45GHz) and LTE (2.6GHz) mobile applications. By appropriately controlling the voltage on the phase shifters, the main beam of the antenna array is steered ±50° and ±52°, for 2.45GHz and 2.6GHz, respectively. Furthermore, the smart antenna array demonstrates a gain of 8.5dBi with 40° 3dB bandwidth in broadside direction, and has more than 10dB side lobe level suppression across the scan. The final stage of the study investigates hardware and software automatic control systems for the smart antenna array. Two microcontrollers PIC18F4550 and LPC1768 are utilised to build the control PCBs. Using the graphical user interfaces provided in this thesis, it is able to configure the beam steering of the smart antenna array, which allows the user to analyse and optimise the signal strength of the received WiFi signals around the mobile device. The design strategies proposed in this thesis contribute to the realisation of adaptable and autonomous smart phone systems

    GigaHertz Symposium 2010

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    Telecommunications system of a CubeSat satellite

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    This Final degree's thesis is done under the UPC-Canadà program in which the author realizes his last degree year in Montréal, Canada, to the Polytechnique de Montréal university under the supervision of Dr. Giovanni Beltrame being part of his laboratory Mistlab and also on the Polyorbite group of students. Polyorbite is an organization that participates in the biannual contest CSDC (Canadian Satellite Design Challenge) that consists on the realization from 0 of a 3U CubeSat by undergraduate and master students. By the start of this thesis on September 2016, the contest was in the middle of the 2014-2016 iteration without having almost nothing on the telecommunication part, having just 2 semesters for design, build and test an entirely telecommunications system, suitable for the satellite purpose, until June 2016 in which the final presentations of the contest took place on Ottawa. The purpose of this thesis is then an early design of a telecommunications system for a CubeSat satellite

    Design of a Multi-sensor and Re-configurable Smart Node for the IoT

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    The rapid deployment of the Internet of Things (IoT) is much dependent on the capacity of the IoT node to be able to self-adapt to the target application. With the increase of sensor networks and diversity of sensors available and with the increasing integration of multiple sensors in a sensor node, it is necessary to develop systems capable of handling all of these sensors with high level of flexibility. These may have different characteristics that provide quite distinct interface requirements, thus giving rise to the need for systems with re-configurable properties. With the implementation of sensor networks in places where energy supply is limited or non-existent, and in situations where technician intervention is expensive, there is a need to exchange conventional energy sources by methods of storage and harvesting of the energy present in the environment, where the sensor node is used (autonomous and renewable energy sources). This thesis will focus on the study and implementation of a family of re-configurable and multi-sensor IoT nodes with special emphasis on the energy storage and power management. It will also focus on the develop of a CAD tool in order to help in the design of CMOS circuits, for the purpose of integrating all the strategies here presented

    The Design, Testing, and Analysis of a Constant Jammer for the Bluetooth Low Energy (BLE) Wireless Communication Protocol

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    The decreasing cost of web-enabled smart devices utilizing embedded processors, sensors, and wireless communication hardware have created an optimal ecosystem for the Internet of Things (IoT). IEEE802.15.4, IEEE802.11ah, WirelessHART, ZigBee Smart Energy, Bluetooth (BT), and Bluetooth Low Energy (BLE) are amongst the most commonly used wireless standards for IoT systems. Each of these standards has tradeoffs concerning power consumption, range of communication, network formation, security, reliability, and ease of implementation. The most widely used standards for IoT are Bluetooth, BLE, and Zigbee. This paper discusses the vulnerabilities in the implementation of the PHY and link layers of BLE. The link layer defines the scheme for establishing a link between two devices. Scanning devices are able to establish communication with other devices that are sending advertising packets. These advertising packets are sent out in a deterministic fashion. The advertising channels for BLE, specified by the PHY layer, are Channels 37, 38, and 39, at center frequencies 2.402, 2.426, and 2.480 GHz, respectively. This scheme for establishing a connection seems to introduce an unintentional gap in the security of the protocol. Creating and transmitting tones with center frequencies corresponding to those of the advertising channels, a victim BLE device will be unable to establish a connection with another BLE device. Jamming a mesh network of BLE devices relies on this same concept. The proposed jamming system is an inexpensive one which utilizes the following hardware. Three individual synthesizers, a microcontroller (MCU), Wilkinson power combiner, power amplifier, and antenna, integrated on a single PCB, are used to transmit a 3-tone signal. Due to the unprecedented nature of the COVID-19 pandemic, necessary adjustments were made to the jammer system design. In the first modified jamming scheme, a single synthesizer evaluation board, power amplifier, and antenna, are used to transmit jamming tones in the form of a frequency hop. Limitations of the frequency hop approach necessitated a second modified scheme. In this second scheme a synthesizer and two Software Defined Radios (SDR), connected to a personal computer, continuously generate three individual jamming tones. The proposed jammer and the modified ones all classify as constant jammers as the transmission of jamming signals is continuous. Both modified jamming schemes are tested. The results of jamming using the second modified scheme validate the objective of simultaneous jamming of the advertising channels of BLE devices. The success of the modified scheme enables the original goal of creating a relatively inexpensive custom PCB for BLE advertising channel jamming. By exploiting the weakness of the BLE protocol, the hope is to have the governing body for Bluetooth, Bluetooth Special Interest Group (SIG), improve security for the future releases of BLE

    Recent Advances in Wireless Communications and Networks

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    This book focuses on the current hottest issues from the lowest layers to the upper layers of wireless communication networks and provides "real-time" research progress on these issues. The authors have made every effort to systematically organize the information on these topics to make it easily accessible to readers of any level. This book also maintains the balance between current research results and their theoretical support. In this book, a variety of novel techniques in wireless communications and networks are investigated. The authors attempt to present these topics in detail. Insightful and reader-friendly descriptions are presented to nourish readers of any level, from practicing and knowledgeable communication engineers to beginning or professional researchers. All interested readers can easily find noteworthy materials in much greater detail than in previous publications and in the references cited in these chapters

    Flexible Receivers in CMOS for Wireless Communication

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    Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block
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