VideoWall Bench: A Benchmark for Evaluating Hardware Accelerated Video Decoding on Linux

VideoWall Bench is a benchmark script for benchmarking video decoding capabilities using hardware acceleration on Linux. Intel has introduced Video Acceleration API (VA-API) which enabled and provides access for graphics hardware to do hardware acceleration. VA API provides a set of video decoders (Codecs) for the H.264 video standards. Multiple video decoding using video wall methodology is a method of benchmarking that be implemented in this script. Using this method, users can really stress the multiple video decoding capabilities of one platform and at the same time measure processor usage for video decoding process. VideoWall Bench benchmark video decoding performance by measuring processor utilization, memory utilization, total frame rate per second (FPS) and time fluctuation in video decoding process. Additionally, VideoWall Bench also includes set

Real-time transmission and storage of video, audio, and health data in emergency and home care situations

The increase in the availability of bandwidth for wireless links, network integration, and the computational power on fixed and mobile platforms at affordable costs allows nowadays for the handling of audio and video data, their quality making them suitable for medical application. These information streams can support both continuous monitoring and emergency situations. According to this scenario, the authors have developed and implemented the mobile communication system which is described in this paper. The system is based on ITU-T H.323 multimedia terminal recommendation, suitable for real-time data/video/audio and telemedical applications. The audio and video codecs, respectively, H.264 and G723.1, were implemented and optimized in order to obtain high performance on the system target processors. Offline media streaming storage and retrieval functionalities were supported by integrating a relational database in the hospital central system. The system is based on low-cost consumer technologies such as general packet radio service (GPRS) and wireless local area network (WLAN or WiFi) for lowband data/video transmission. Implementation and testing were carried out for medical emergency and telemedicine application. In this paper, the emergency case study is described

Performance analysis of MPEG-4 decoder and encoder

© 2002 Croatian Soc. Electronics in Marine-ELMAR. A performance analysis of MPEG-4 encoder and decoder programs on a standard personal computer is presented. The paper first describes the MPEG-4 computational load and discusses related works, then outlines the performance analysis. Experimental results show that while the decoder program can be easily executed in real time, the encoder requires execution times in the order of seconds per frame which call for substantial optimisation to satisfy real-time constraints

Complexity Control for H.264 Video Encoding over Power-Scalable Embedded Systems

Abstract-This work proposes a complexity-control algorithm that efficiently utilizes encoding tools of an H.264 video coding system under different power status. Experiments performed on a power-scalable embedded system 1 reveal the excellent ratedistortion performance with various power constraints. Specifically, the power consumption can be adjusted around 77% to 100% with PSNR degradation within 1.08dB at the same bit rate

Indexing, browsing and searching of digital video

Video is a communications medium that normally brings together moving pictures with a synchronised audio track into a discrete piece or pieces of information. The size of a “piece ” of video can variously be referred to as a frame, a shot, a scene, a clip, a programme or an episode, and these are distinguished by their lengths and by their composition. We shall return to the definition of each of these in section 4 this chapter. In modern society, video is ver

VideoWall Bench: A Benchmark for Evaluating Hardware Accelerated Video Decoding on Linux

VideoWall Bench is a benchmark script for benchmarking video decoding capabilities using hardware acceleration on Linux. Intel has introduced Video Acceleration API (VA-API) which enabled and provides access for graphics hardware to do hardware acceleration. VA API provides a set of video decoders (Codecs) for the H.264 video standards. Multiple video decoding using video wall methodology is a method of benchmarking that be implemented in this script. Using this method, users can really stress the multiple video decoding capabilities of one platform and at the same time measure processor usage for video decoding process. VideoWall Bench benchmark video decoding performance by measuring processor utilization, memory utilization, total frame rate per second (FPS) and time fluctuation in video decoding process. Additionally, VideoWall Bench also includes set

Exploring Processor and Memory Architectures for Multimedia

Multimedia has become one of the cornerstones of our 21st century society and, when combined with mobility, has enabled a tremendous evolution of our society. However, joining these two concepts introduces many technical challenges. These range from having sufficient performance for handling multimedia content to having the battery stamina for acceptable mobile usage. When taking a projection of where we are heading, we see these issues becoming ever more challenging by increased mobility as well as advancements in multimedia content, such as introduction of stereoscopic 3D and augmented reality. The increased performance needs for handling multimedia come not only from an ongoing step-up in resolution going from QVGA (320x240) to Full HD (1920x1080) a 27x increase in less than half a decade. On top of this, there is also codec evolution (MPEG-2 to H.264 AVC) that adds to the computational load increase. To meet these performance challenges there has been processing and memory architecture advances (SIMD, out-of-order superscalarity, multicore processing and heterogeneous multilevel memories) in the mobile domain, in conjunction with ever increasing operating frequencies (200MHz to 2GHz) and on-chip memory sizes (128KB to 2-3MB). At the same time there is an increase in requirements for mobility, placing higher demands on battery-powered systems despite the steady increase in battery capacity (500 to 2000mAh). This leaves negative net result in-terms of battery capacity versus performance advances. In order to make optimal use of these architectural advances and to meet the power limitations in mobile systems, there is a need for taking an overall approach on how to best utilize these systems. The right trade-off between performance and power is crucial. On top of these constraints, the flexibility aspects of the system need to be addressed. All this makes it very important to reach the right architectural balance in the system. The first goal for this thesis is to examine multimedia applications and propose a flexible solution that can meet the architectural requirements in a mobile system. Secondly, propose an automated methodology of optimally mapping multimedia data and instructions to a heterogeneous multilevel memory subsystem. The proposed methodology uses constraint programming for solving a multidimensional optimization problem. Results from this work indicate that using today’s most advanced mobile processor technology together with a multi-level heterogeneous on-chip memory subsystem can meet the performance requirements for handling multimedia. By utilizing the automated optimal memory mapping method presented in this thesis lower total power consumption can be achieved, whilst performance for multimedia applications is improved, by employing enhanced memory management. This is achieved through reduced external accesses and better reuse of memory objects. This automatic method shows high accuracy, up to 90%, for predicting multimedia memory accesses for a given architecture

Evaluation of multiple slices and tiles in HEVC video encoding

Σημείωση: διατίθεται συμπληρωματικό υλικό σε ξεχωριστό αρχείο

Architekturkonzepte für prozessorbasierte MPEG Videodecoder mit Schwerpunkt für mobile Anwendungen

Mobile Endgeräte basieren z. Zt. auf Systemen (System on a Chip), deren Hauptfunktionalität durch den Einsatz entsprechender Software auf eingebetteten Prozessoren gebildet wird. Aufgrund der immer kürzeren Innovationszyklen kommt der softwarebasierten Umsetzung von Applikationen für eingebettete Systeme damit eine steigende Bedeutung zu. Im Bereich der mobilfunkgestützten Anwendungen sind in zunehmendem Maße auch Multimediaapplikationen vorzufinden, die bis vor kurzem noch leistungsfähigen Systemen, wie z.B. Desktop-PCs oder dedizierten Implementierungen in Form spezieller ASICs, vorbehalten waren. Hierzu zählen auch Anwendungen, die auf entsprechenden Standards basierend, die echtzeitfähige Übertragung von Bewegtbilddaten unterstützen, wie z.B. Videotelefonie oder Broadcastdienste. Dem hohen Rechenleistungsbedarf echtzeitkritischer Multimediaapplikationen stehen hierbei jedoch die relativ leistungsschwachen Prozessoren eingebetteter Systeme gegenüber. Im Bereich der Videocodierung für Mobilfunkanwendungen hat sich der MPEG-4-Standard weitgehend etabliert und wird hier stellvertretend für alle weiteren MPEG-Videostandards ausführlich beschrieben und analysiert. Die vorliegende Arbeit befasst sich daher im Kern mit dem Entwurf einer speziellen Befehls-satz- und Coprozessorerweiterung für MPEG-4-basierte Videodecoderalgorithmen, womit ein Performancegewinn von ca. 50% gegenüber einer reinen Softwareimplementierung erzielt wird. Die Erweiterungen sind in ihrer Definition generisch und daher nicht auf einen speziellen Prozessortyp zugeschnitten. Im vorliegenden Falle wird eine für Mobilfunkterminals typische RISC-Architektur herangezogen, um die Leistungsfähigkeit unter Beweis zu stellen und den Einsatz in eingebetteten Systemen aufzuzeigen. Die einzelnen Konzepte werden auf Basis einer Algorithmenanalyse hergeleitet, wobei erst eine Beschreibung der generischen Erweiterung erfolgt und anschließend die Integration in den verwendeten Prozessorkern unter Verwendung der Hardwarebeschreibungssprache VHDL beschrieben wird. Für die Bemessung des Echtzeitverhaltens wird im Rahmen der Arbeit ein spezieller Profiler entworfen, der unter anderem auch die Untersuchung und Optimierung des Speicherzugriffs-verhaltens gestattet. Mit Hilfe des Profilers werden Messungen durchgeführt, die den Rechenzeitgewinn der jewei-ligen Algorithmenteile unter Zuhilfenahme der implementierten Optimierungen aufzeigen. Ebenso wird ein Vergleich der Leistungsfähigkeit der vorgestellten Architektur mit gängigen Prozessorarchitekturen, wie Superskalare und VLIW-Prozessoren, vorgenommen. Hierbei wird ermittelt, dass das entwickelte Konzept ähnliche Resultate erbringt wie die vergleichsweise komplexeren Prozessoren. Neben der Leistungsfähigkeit steht auch die Ermittlung des Flächenbedarfs im Falle einer CMOS Gate-Array-basierten Implementierung zur Diskussion und wird ebenfalls für jede einzelne Erweiterung dargestellt