Development of new heat sink technology for high-density microprocessors

This study investigates the performance of existing heat sinks and compares it with two heat-exchanger prototypes: aluminum-foam heat sink and PCM (phase-change material)-filled heat sink. Kapton flexible heaters are used to replicate the heat produced by a computer\u27s CPU (central processing unit). A number of thermocouples are connected between the heater and the heat sink being used to measure the component\u27s temperature. The thermocouples are also connected to a data acquisition card to collect the data using a LabVIEW program. The values obtained are compared to data published in literature to validate the experiments and the setup. This setup is then utilized to test the new heat exchangers and compare their performance to that of the existing heat sinks

A high-performance inner-product processor for real and complex numbers.

A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is investigated in this dissertation. This scheme decreases the number of partial products to 50%, while achieving better speed and area performance, as well as providing pipeline extension opportunities. When modified Booth coding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require real and/or complex numbers inner-product arithmetic, such as digital filters, correlation and convolution. This design is well suited for VLSI implementation and can also be embedded as an inner-product core inside a general purpose or DSP FPGA-based processor. Dynamic control of the computing structure permits different computations, such as a variety of inner-product real and complex number computations, parallel multiplication for real and complex numbers, and real and complex number division. The same structure can also be controlled to accept redundant binary number inputs for multiplication and inner-product computations. An improved 2's-complement to redundant binary converter is also presented

Optimización de una implementación JPEG teniendo en cuenta la arquitectura actual de los procesadores

Creemos conveniente proponer trabajos fin de carrera con el objetivo de que los estudiantes comprueben que pueden mejorar ostensiblemente las prestaciones de sus programas en poco tiempo aplicando los conocimientos sobre arquitectura de computadores que han ido adquiriendo a lo largo de la titulación. Mostrando los resultados obtenidos en estos trabajos a estudiantes de diferentes cursos de la titulación, pretendemos incrementar su motivación en las materias de arquitectura. Aquí se muestra el incremento en prestaciones obtenido, aprovechando la arquitectura actual de los computadores, en una implementación de descodificador JPEG. Para la mejora de prestaciones, se propone seguir un proceso iterativo de varios pasos

Implementation of an FPGA based accelerator for virtual private networks.

Cheung Yu Hoi Ocean.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 65-70).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Aims --- p.2Chapter 1.3 --- Contributions --- p.3Chapter 1.4 --- Thesis Outline --- p.3Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4Chapter 2.3 --- Secure Virtual Private Network --- p.6Chapter 2.4 --- LibDES --- p.9Chapter 2.5 --- FreeS/WAN --- p.9Chapter 2.6 --- Commercial VPN solutions --- p.9Chapter 2.7 --- Summary --- p.11Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12Chapter 3.1 --- Introduction --- p.12Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16Chapter 3.3 --- The IDEA Algorithm --- p.17Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20Chapter 3.3.2 --- Previous work on IDEA --- p.21Chapter 3.4 --- Block Cipher Modes of operation --- p.23Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27Chapter 3.6 --- Pilchard --- p.30Chapter 3.6.1 --- Memory Cache Control Mode --- p.31Chapter 3.7 --- Electronic Design Automation Tools --- p.32Chapter 3.8 --- Summary --- p.33Chapter 4 --- ImplementationChapter 4.1 --- Introduction --- p.36Chapter 4.1.1 --- Hardware Platform --- p.36Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36Chapter 4.1.3 --- Pilchard Software --- p.38Chapter 4.2 --- DES in ECB mode --- p.39Chapter 4.2.1 --- Hardware --- p.39Chapter 4.2.2 --- Software Interface --- p.40Chapter 4.3 --- DES in CBC mode --- p.42Chapter 4.3.1 --- Hardware --- p.42Chapter 4.3.2 --- Software Interface --- p.42Chapter 4.4 --- Triple-DES in CBC mode --- p.45Chapter 4.4.1 --- Hardware --- p.45Chapter 4.4.2 --- Software Interface --- p.45Chapter 4.5 --- IDEA in ECB mode --- p.48Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48Chapter 4.5.2 --- Hardware --- p.48Chapter 4.5.3 --- Software Interface --- p.50Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53Chapter 4.9 --- Summary --- p.54Chapter 5 --- Results --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Benchmarking environment --- p.55Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56Chapter 5.3.1 --- Performance of Triple-DES core --- p.55Chapter 5.3.2 --- Performance of IDEA core --- p.58Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59Chapter 5.4.1 --- Triple-DES --- p.59Chapter 5.4.2 --- IDEA --- p.60Chapter 5.5 --- Summary --- p.61Chapter 6 --- Conclusion --- p.62Chapter 6.1 --- Future development --- p.63Bibliography --- p.6

Android Application Development for the Intel Platform

Computer scienc