On the Error Resilience of Ordered Binary Decision Diagrams

Ordered Binary Decision Diagrams (OBDDs) are a data structure that is used in an increasing number of fields of Computer Science (e.g., logic synthesis, program verification, data mining, bioinformatics, and data protection) for representing and manipulating discrete structures and Boolean functions. The purpose of this paper is to study the error resilience of OBDDs and to design a resilient version of this data structure, i.e., a self-repairing OBDD. In particular, we describe some strategies that make reduced ordered OBDDs resilient to errors in the indexes, that are associated to the input variables, or in the pointers (i.e., OBDD edges) of the nodes. These strategies exploit the inherent redundancy of the data structure, as well as the redundancy introduced by its efficient implementations. The solutions we propose allow the exact restoring of the original OBDD and are suitable to be applied to classical software packages for the manipulation of OBDDs currently in use. Another result of the paper is the definition of a new canonical OBDD model, called {\em Index-resilient Reduced OBDD}, which guarantees that a node with a faulty index has a reconstruction cost $O(k)$, where $k$ is the number of nodes with corrupted index

Proof Complexity and Beyond

Proof complexity is a multi-disciplinary intellectual endeavor that addresses questions of the general form “how difficult is it to prove certain mathematical facts?” The current workshop focused on recent advances in our understanding of logic-based proof systems and on connections to algorithms, geometry and combinatorics research, such as the analysis of approximation algorithms, or the size of linear or semidefinite programming formulations of combinatorial optimization problems, to name just two important examples

Efficient local search for Pseudo Boolean Optimization

Algorithms and the Foundations of Software technolog

Synthesis for circuit reliability

textElectrical and Computer Engineerin

Probabilistic representation and manipulation of Boolean functions using free Boolean diagrams

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 145-149).by Amelia Huimin Shen.Ph.D

Synthèse d'orchestrateur pour la composition de services

La composition de comportement est un aspect important dans beaucoup de domaines, surtout dans la programmation orientée service (Service Oriented Computing) et dans les systèmes Multi-agents. L'objectif est d'orchestrer le comportement des différents modules, modelisés par des système de transitions étiquetés (abelled transition systems - LTS), pour satisfaire une specification but, de même modelisé comme LTS. Un problème majeur qu'on trouve dans la plupart des approches, est le nombre élevé d'états. L'objectif de cette thèse est de développer des méthodes efficaces pour résoudre le problème de composition de comportement.D'abord on analyse le cas où toutes les actions sont observables. Nous developpons ensuite une caractérisation de l'existence d'une solution en terme d'une relation entre les différentes composantes d'une part et la specification but d'autre part. En utilisant cette caractérisation , nous développons un algorithme qui trouve à la volée une solution au problème si cette dernière existe. Nous démontrons que l'algorithme est correct et sa complexité est polynomiale par rapport à la taille des composants. Nous prouvons également que l'algorithme est robuste par rapport à l'échec d'un des composants. Ensuite, nous proposons une méthode d'abstraction qui réduit considérablement le nombre d'états. Cette abstraction est utilisée comme outil heuristique qui accélère la recherche. Finalement, nous développons une caractérisation de l'existence d'une solution dans le cas d'observation partielle. Cette caractérisation est elaborée en introduisant le concept de contrabilité. Nous démontrons qu'une solution existe si et seulement si les composantes sont controlables par rapport au but. Nous developpons un algorithme pour trouver la relation de controlabilité à la volée. La complexité de l'algorithme est EXPTIME en terme de la taille des composants.The behavior composition problem is an important aspect in many fields, especially in Service Oriented Computing and in Multi-agent systems. The basic objective is to orchestrate the behavior of the different available components, modeled as labeled transition systems (LTS), in order to satisfy a given goal specification, also modeled as an LTS . A major concern has been the large state space of typical situations which made existing approaches very compute intensive. The aim of this thesis is to develop efficient methods to solve the behavior composition problem. First we study the case when all actions are observable. We develop a characterization of the existence of a solution in term of existence of a relation between the different available components, considered as a single system, on one hand and the goal specification on the other. Using that characterization we develop an on-the-fly algorithm that finds a solution to the problem when one exists. The algorithm is shown to be correct and has polynomial complexity with the respect to the size of the components. We also show that the algorithm is robust with respect to component failure. Then we propose an abstraction method that reduces drastically the number of states. We show that the non-existence of a solution in the abstracted systems implies the non-existence of solution in the original system. Also the result of the abstraction is used as an input to the above algorithm for use as a heuristic to speed up the search. Finally, we develop a characterization of the behavior composition problem in the case of partial observation by using the concept of controllability. We show that a solution to the composition problem with partial observation exists if and only if the components are controllable with respect to the goal specification. We also develop an on-the-fly algorithm to compute the controllability of the system. The complexity of the algorithm is EXPTIME in the size of the components

Logic Synthesis for Established and Emerging Computing

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported

New Data Structures and Algorithms for Logic Synthesis and Verification

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effect Transistor (FET) dimensions enabled the semiconductor industry to fabricate digital systems with higher circuit density at reduced costs. To keep pace with technology, EDA tools are challenged to handle both digital designs with growing functionality and device models of increasing complexity. Nevertheless, whereas the downscaling of CMOS technology is requiring more complex physical design models, the logic abstraction of a transistor as a switch has not changed even with the introduction of 3D FinFET technology. As a consequence, modern EDA tools are fine tuned for CMOS technology and the underlying design methodologies are based on CMOS logic primitives, i.e., negative unate logic functions. While it is clear that CMOS logic primitives will be the ultimate building blocks for digital systems in the next ten years, no evidence is provided that CMOS logic primitives are also the optimal basis for EDA software. In EDA, the efficiency of methods and tools is measured by different metrics such as (i) the result quality, for example the performance of a digital circuit, (ii) the runtime and (iii) the memory footprint on the host computer. With the aim to optimize these metrics, the accordance to a specific logic model is no longer important. Indeed, the key to the success of an EDA technique is the expressive power of the logic primitives handling and solving the problem, which determines the capability to reach better metrics. In this thesis, we investigate new logic primitives for electronic design automation tools. We improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. We develop synthesis tools exploiting the majority and biconditional expressiveness. Our tools show strong results as compared to state-of-the-art academic and commercial synthesis tools. Indeed, we produce the best results for several public benchmarks. On top of the enhanced synthesis power, our methods are the natural and native logic abstraction for circuit design in emerging nanotechnologies, where majority and biconditional logic are the primitive gates for physical implementation. We accelerate formal methods by (i) studying properties of logic circuits and (ii) developing new frameworks for logic reasoning engines. We prove non-trivial dualities for the property checking problem in logic circuits. Our findings enable sensible speed-ups in solving circuit satisfiability. We develop an alternative Boolean satisfiability framework based on majority functions. We prove that the general problem is still intractable but we show practical restrictions that can be solved efficiently. Finally, we focus on reversible logic where we propose a new equivalence checking approach. We exploit the invertibility of computation and the functionality of reversible gates in the formulation of the problem. This enables one order of magnitude speed up, as compared to the state-of-the-art solution. We argue that new approaches to solve EDA problems are necessary, as we have reached a point of technology where keeping pace with design goals is tougher than ever