Design of an Ultra-Low Power RTC for the IoT

The Internet of Things is growing at an exponential rate. This new perception of reality is being researched even further nowadays because society is starting to develop an interest on these technologies. Market potential is increasing even further, since the foreseeable implementations are diverse and still to be detected. The future applications for the IoT are enthusiastic and they will increase the overall quality of life of the citizens of the world. Developing a component that is crucial for the sustainability of this implementation is the task that truly motivates the intended work for this project. Designing the full-custom circuitry and physical layout of a Real Time Clock becomes a job that has a lot of minor details that need considerable attention. These technicalities truly tone the developers skill and knowledge of different design principles. Besides, developing the solution using subthreshold CMOS techniques will put emphasis on different technological procedures. Producing devices that are heavily dependent on PVT variations, operational frequency and power consumption define this new task, that needs a stable approach to all these diverse figure of merits, even though they are all interconnected. The study and understanding of these different approaches allows for a more complex in depth grasp of this recent intriguing proceedings

Low power CMOS IC, biosensor and wireless power transfer techniques for wireless sensor network application

The emerging field of wireless sensor network (WSN) is receiving great attention due to the interest in healthcare. Traditional battery-powered devices suffer from large size, weight and secondary replacement surgery after the battery life-time which is often not desired, especially for an implantable application. Thus an energy harvesting method needs to be investigated. In addition to energy harvesting, the sensor network needs to be low power to extend the wireless power transfer distance and meet the regulation on RF power exposed to human tissue (specific absorption ratio). Also, miniature sensor integration is another challenge since most of the commercial sensors have rigid form or have a bulky size. The objective of this thesis is to provide solutions to the aforementioned challenges

Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation

Sympathetic ground state cooling and coherent manipulation with two-ion-crystals

We have cooled a two-ion-crystal to the ground state of its collective modes of motion. Laser cooling, more specific resolved sideband cooling is performed sympathetically by illuminating only one of the two $^{40}$Ca$^+$ ions in the crystal. The heating rates of the motional modes of the crystal in our linear trap have been measured, and we found them considerably smaller than those previously reported by Q. Turchette {\em et. al.} Phys. Rev. A 61, 063418 (2000) in the case of trapped $^9$Be$^+$ ions. After the ground state is prepared, coherent quantum state manipulation of the atomic population can be performed. Within the coherence time, up to 12 Rabi oscillations are observed, showing that many coherent manipulations can be achieved. Coherent excitation of each ion individually and ground state cooling are important tools for the realization of quantum information processing in ion traps

Data based identification and prediction of nonlinear and complex dynamical systems

We thank Dr. R. Yang (formerly at ASU), Dr. R.-Q. Su (formerly at ASU), and Mr. Zhesi Shen for their contributions to a number of original papers on which this Review is partly based. This work was supported by ARO under Grant No. W911NF-14-1-0504. W.-X. Wang was also supported by NSFC under Grants No. 61573064 and No. 61074116, as well as by the Fundamental Research Funds for the Central Universities, Beijing Nova Programme.Peer reviewedPostprin

MorphIC: A 65-nm 738k-Synapse/mm2^2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.Comment: This document is the paper as accepted for publication in the IEEE Transactions on Biomedical Circuits and Systems journal (2019), the fully-edited paper is available at https://ieeexplore.ieee.org/document/876400

On evaluating temperature as observable for CMOS technology variability

The temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures of merit (FoM) of some digital and analog circuits and the power dissipated by such circuits. It is shown that in some cases, a strong correlation exists between the variation of the circuit FoM and the variation of the dissipated power. Since local temperature increase at the silicon surface close to the circuit linearly depends on dissipated power, the results show that temperature can be considered as an observable magnitude for CMOS technology variability monitoring.Postprint (published version

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Design of an Ultra-Wideband Frequency-Modulated Continuous Wave Short Range Radar System for Extending Independent Living

Falls in the disabled and elderly people have been a cause of concern as they can be immobilized by the fall and have no way to contact others and seek assistance. The proposed frequency modulated continuous wave (FMCW) short range radar (SRR) system, which uses ultra-wideband (UWB) signals can provide immediate assistance by monitoring and detecting fall events. The unique characteristics of this system allow for a frequency-based modulation system to carry out triangulation and sense the location of the fall through the usage of a continuous chirp signal that linearly sweeps frequency. This project focuses on the development, design and simulation of a ring oscillator that exhibits the frequency modulated signal on a single integrated circuit chip. The ring oscillator is controlled by a voltage ramp signal generator and a voltage to current (V-I) converter. The circuit is designed in Cadence using TSMC 180nm process technology and operates in the frequency range of 3.409 GHz to 5.349 GHz with a spectral bandwidth of 1.94 GHz, which meets the Federal Communications Commission’s standards for unlicensed ultra-wideband transmissions