FPGA BASED PARALLEL IMPLEMENTATION OF STACKED ERROR DIFFUSION ALGORITHM

Digital halftoning is a crucial technique used in digital printers to convert a continuoustone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This thesis focuses on the development and design of a parallel scalable hardware architecture for high performance implementation of a high quality Stacked Error Diffusion algorithm. The algorithm is described in ‘C’ and requires a significant processing time when implemented on a conventional CPU. Thus, a new hardware processor architecture is developed to implement the algorithm and is implemented to and tested on a Xilinx Virtex 5 FPGA chip. There is an extraordinary decrease in the run time of the algorithm when run on the newly proposed parallel architecture implemented to FPGA technology compared to execution on a single CPU. The new parallel architecture is described using the Verilog Hardware Description Language. Post-synthesis and post-implementation, performance based Hardware Description Language (HDL), simulation validation of the new parallel architecture is achieved via use of the ModelSim CAD simulation tool

Video data modulation study, volume 1 Final report

Video data modulation technique

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Efficient architectures for multidimensional discrete transforms in image and video processing applications

PhD ThesisThis thesis introduces new image compression algorithms, their related architectures and data transforms architectures. The proposed architectures consider the current hardware architectures concerns, such as power consumption, hardware usage, memory requirement, computation time and output accuracy. These concerns and problems are crucial in multidimensional image and video processing applications. This research is divided into three image and video processing related topics: low complexity non-transform-based image compression algorithms and their architectures, architectures for multidimensional Discrete Cosine Transform (DCT); and architectures for multidimensional Discrete Wavelet Transform (DWT). The proposed architectures are parameterised in terms of wordlength, pipelining and input data size. Taking such parameterisation into account, efficient non-transform based and low complexity image compression algorithms for better rate distortion performance are proposed. The proposed algorithms are based on the Adaptive Quantisation Coding (AQC) algorithm, and they achieve a controllable output bit rate and accuracy by considering the intensity variation of each image block. Their high speed, low hardware usage and low power consumption architectures are also introduced and implemented on Xilinx devices. Furthermore, efficient hardware architectures for multidimensional DCT based on the 1-D DCT Radix-2 and 3-D DCT Vector Radix (3-D DCT VR) fast algorithms have been proposed. These architectures attain fast and accurate 3-D DCT computation and provide high processing speed and power consumption reduction. In addition, this research also introduces two low hardware usage 3-D DCT VR architectures. Such architectures perform the computation of butterfly and post addition stages without using block memory for data transposition, which in turn reduces the hardware usage and improves the performance of the proposed architectures. Moreover, parallel and multiplierless lifting-based architectures for the 1-D, 2-D and 3-D Cohen-Daubechies-Feauveau 9/7 (CDF 9/7) DWT computation are also introduced. The presented architectures represent an efficient multiplierless and low memory requirement CDF 9/7 DWT computation scheme using the separable approach. Furthermore, the proposed architectures have been implemented and tested using Xilinx FPGA devices. The evaluation results have revealed that a speed of up to 315 MHz can be achieved in the proposed AQC-based architectures. Further, a speed of up to 330 MHz and low utilisation rate of 722 to 1235 can be achieved in the proposed 3-D DCT VR architectures. In addition, in the proposed 3-D DWT architecture, the computation time of 3-D DWT for data size of 144×176×8-pixel is less than 0.33 ms. Also, a power consumption of 102 mW at 50 MHz clock frequency using 256×256-pixel frame size is achieved. The accuracy tests for all architectures have revealed that a PSNR of infinite can be attained

Optical Communication

Optical communication is very much useful in telecommunication systems, data processing and networking. It consists of a transmitter that encodes a message into an optical signal, a channel that carries the signal to its desired destination, and a receiver that reproduces the message from the received optical signal. It presents up to date results on communication systems, along with the explanations of their relevance, from leading researchers in this field. The chapters cover general concepts of optical communication, components, systems, networks, signal processing and MIMO systems. In recent years, optical components and other enhanced signal processing functions are also considered in depth for optical communications systems. The researcher has also concentrated on optical devices, networking, signal processing, and MIMO systems and other enhanced functions for optical communication. This book is targeted at research, development and design engineers from the teams in manufacturing industry, academia and telecommunication industries

Proceedings of the EAA Spatial Audio Signal Processing symposium: SASP 2019

International audienc

An Investigation into the Implementation and Performance of Spectrally Shaped Orthogonal Frequency Division Multiplex

Orthogonal Frequency Division Multiplex (OFDM) is a flexible, robust multi-carrier modulation scheme. The orthogonal spectral shaping and spacing of OFDM sub-carriers ensure that their spectra can be over-lapped without leading to undesirable inter-carrier interference. Conventional OFDM systems have non-band limited Sinc(x) shaped subcarrier spectra. An alternative form of OFDM, referred to hereafter as Spectrally Shaped OFDM, employs band limited Nyquist shaped sub-carrier spectra. The research described in this thesis investigates the strengths and weaknesses of Spectrally Shaped OFDM as a potential modulation scheme for future mobile radio applications. From this research a novel Digital Signal Processing architecture for modulating and demodulating Spectrally Shaped OFDM sub-carriers has been derived which exploits the combination of a complex Discrete Fourier Transform (DFT) and PolyPhase Network (PPN) filter. This architecture is shown to significantly reduce the minimum number of computations required per symbol compared to previous designs. Using a custom coded computer simulation, the effects of varying the key parameters of the novel architecture's PolyPhase Filter (PPN) filter an the overall system complexity, spectral performance and system signal-to-distortion have been extensively studied. From these studies it is shown that compared to similar conventional OFDM systems, Spectrally Shaped OFDM systems possess superior out-of-band spectral qualities but significantly worse Peak-to-Average-Power-Ratio (PAPR) envelope performance. lt is also shown that the absolute value of the end PPN filter coefficients (dependent on the roll-off factor of the sub-carrier spectral shaping) dictate the system signal-to-distortion ratio when no time-domain windowing of the PPN filter coefficients is applied. Finally the effects of a both time and frequency selective fast fading channels on the modulation scheme's uncoded Bit Error Rate (BER) versus Signal-to-Noise (SNR) performance are simulated. The results obtained indicate that Spectrally Shaped OFDM is more robust (lower BER) to frequency-selective fading than time-selective fading