Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Methodologies For Thermal Analysis In Single Die And Stacked Dies Electronic Packaging

Thermal analysis in single die and stacked dies electronic packaging for portable communication devices is very important due to lack of real estate for active cooling. Recent research had focused on active cooling and neglected the low cost passive cooling by optimizing the architecture of package structure and material selection. Stacked dies electronic package is an economical and good electrical performance innovation but inherent thermal problems which caused by thermal crosstalk. Recent methodology for numerical method and measurement method for thermal analysis in QFN and stacked dies LBGA is labor intensive, needs huge amount of investment and requires expert’s knowledge

Development of convective reflow-projection moire warpage measurement system and prediction of solder bump reliability on board assemblies affected by warpage

Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may cause serious reliability problems. In this research, a convective reflow and projection moire warpage measurement system was developed. The system is the first real-time, non-contact, and full-field measurement system capable of measuring PWB/PWBA/chip package warpage with the projection moire technique during different thermal reflow processes. In order to accurately simulate the reflow process and to achieve the ideal heating rate, a convective heating system was designed and integrated with the projection moire system. An advanced feedback controller was implemented to obtain the optimum heating responses. The developed system has the advantages of simulating different types of reflow processes, and reducing the temperature gradients through the PWBA thickness to ensure that the projection moire system can provide more accurate measurements. Automatic package detection and segmentation algorithms were developed for the projection moire system. The algorithms are used for automatic segmentation of the PWB and assembled packages so that the warpage of the PWB and chip packages can be determined individually. The effect of initial PWB warpage on the fatigue reliability of solder bumps on board assemblies was investigated using finite element modeling (FEM) and the projection moire system. The 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different chip packages mounted on PWBs. The simulation results were validated and correlated with the experimental results obtained using the projection moire system and accelerated thermal cycling tests. Design of experiments and an advanced prediction model were generated to predict solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials. This study led to a better understanding of the correlation between PWB warpage and solder bump thermomechanical reliability on board assemblies.Ph.D.Committee Chair: Dr. Ume, I. Charles; Committee Member: Dr. Book, Wayne; Committee Member: Dr. Kim, Yeong; Committee Member: Dr. Pan, Jiahui; Committee Member: Dr. Sitaraman, Suresh; Committee Member: Dr. Wu, C. F. Jef

Fundamental Studies of Tin Whiskering in Microelectronics Finishes

Fundamental Studies of Tin Whiskering in Microelectronics Finishes Abstract Common electronics materials, such as tin, copper, steel, and brass, are ambient reactive under common use conditions, and as such are prone to corrosion. During the early 1940s, reports of failures due to electrical shorting of components caused by `whisker' (i.e., filamentary surface protrusion) growth on many surface types - including the aforementioned metals - began to emerge. Lead alloying of tin (3-10% by weight, typically in the eutectic proportion) eliminated whiskering risk for decades, until the July 2006 adoption of the Restriction of Hazardous Substances (RoHS) directive was issued by the European Union. This directive, which has since been adopted by California and parts of China, severely restricted the use of lead (<1000 ppm) in all electrical and electronics equipment being placed on the EU market, imposing the need for developing reliable new "lead-free" alternatives to SnPb. In spite of the abundance of modern-day anecdotes chronicling whisker-related failures in satellites, nuclear power stations, missiles, pacemakers, and spacecraft navigation equipment, pure tin finishes are still increasingly being employed today, and the root cause(s) of tin whiskering remains elusive. This work describes a series of structured experiments exploring the fundamental relationships between the incidence of tin whiskering (as dependent variable) and numerous independent variables. These variables included deposition method (electroplating, electroless plating, template-based electrochemical synthesis, and various physical vapor deposition techniques, including resistive evaporation, electron beam evaporation, and sputtering), the inclusion of microparticles and organic contamination, the effects of sample geometry, and nanostructuring. Key findings pertain to correlations between sample geometry and whisker propensity, and also to the stress evolution across a series of 4"-diameter silicon wafers of varying thicknesses with respect to the degree of post-metallization whiskering. Regarding sample geometry, it was found that smaller, thinner substrates displayed a more rapid onset of whiskering immediately following metallization. Changes in wafer-level stress were not found to correlate with whiskering morphology (number, density, length) after 6 weeks of aging. This result points either to the irrelevance of macrostress in the substrate/film composite, or to a difference in whiskering mechanism for rigid substrates (whose stress gradient over time is significant) when compared with thinner, flexible susbtrates (whose stress is less variable with time). Organic contamination was found to have no appreciable effect when explicitly introduced. Furthermore, electron-beam evaporated films whiskered more readily than films deposited via electroplating from baths containing organic "brighteners." Beyond such findings, novel in themselves, our work is also unique in that we emphasize the "clean" deposition of tin (with chromium adhesion layers and copper underlayers) by vacuum-based physical vapor deposition, to circumvent the question of contamination entirely. By employing silicon substrates exclusively, we have distinguished ourselves from other works (which, for example, use copper coupons fabricated from rolled shim stock) because we have better sample-to-sample consistency in terms of material properties, machinability, and orientation

Board level drop testing of advanced IC packaging

Master'sMASTER OF ENGINEERIN

PCB Quality Metrics that Drive Reliability (PD 18)

Risk based technology infusion is a deliberate and systematic process which defines the analysis and communication methodology by which new technology is applied and integrated into existing and new designs, identifies technology development needs based on trends analysis and facilitates the identification of shortfalls against performance objectives. This presentation at IPC Works Asia Aerospace 2019 Events provides the audience a snapshot of quality variations in printed wiring board quality, as assessed, using experiences in processing and risk analysis of PWB structural integrity coupons. The presentation will focus on printed wiring board quality metrics used, the relative type and number of non-conformances observed and trend analysis using statistical methods. Trend analysis shows the top five non-conformances observed across PWB suppliers, the root cause(s) behind these non-conformance and suggestions of mitigation plans. The trends will then be matched with the current state of the PWB supplier base and its challenges and opportunities. The presentation further discusses the risk based SMA approaches and methods being applied at GSFC for evaluating candidate printed wiring board technologies which promote the adoption of higher throughput and faster processing technology for GSFC missions

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH

High-frequency characterization of embedded components in printed circuit boards

The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

Compliant Chip-to-Package Interconnects for Wafer Level Packaging

Ph.DDOCTOR OF PHILOSOPH

Effect of Dynamic Flexural Loading on the Durability and Failure Site of Solder Interconnects in Printed Wiring Assemblies

This dissertation investigates the durability of solder interconnects of area array packages mounted on Printed Wiring Assemblies (PWAs) subjected to dynamic flexural loads, using a combination of testing, empirical curve fitting and mechanistic modeling. Dynamic 4-point bend tests are conducted on a drop tower and with an impact pendulum. Failure data is collected and an empirical rate-dependent durability model, based on mechanistic considerations, is developed to estimate the fatigue failure envelopes of the solder, as a function of solder strain and strain-rate. The solder plastic strain histories are obtained from the PWA flexural strain and strain rate, using transfer functions developed from 3D transient Finite Element Analysis (FEA) with rate-dependent solder material properties. The test data also shows the existence of multiple competing failure sites: solder, copper trace, PWB under solder pads, and layers of intermetallic compound (IMC) between the solder and solder pads. The failures in the IMC layers are found to be either in the bulk of the IMC layers or at the interface between different species of IMC layers. The dominant failure site is found to be strongly dependent on the loading conditions. The empirical model is demonstrated for solder failures as well as Cu trace failures, and the transition between their competing failure envelopes is identified. This dissertation then focuses in detail on two of these competing failure sites: (i) the solder and (ii) the interface between two IMC layers. A strain-range fatigue damage model, based on strain-rate hardening and exhaustion of ductility, is used to quantify the durability and estimate the fatigue constants of the solder for high strain rates of loading. Interfacial fracture mechanics is used to estimate the damage accumulation rates at the IMC interface. The IMC failure model and the solder failure model provide a mechanistic perspective on the failure site transitions. Durability metrics, based on the mechanics of these two failure mechanisms, are used to quantify the competing damage accumulation rates at the two failure sites for a given loading condition. The results not only identify which failure site dominates but also provide estimate of the durability of the solder interconnect. The test data shows good correlation with the model predictions. The test vehicles used in this study consist of PWAs with Sn37Pb solder interconnects. But the proposed test methodologies and mechanistic models are generic enough to be easily extended to other emerging lead free solder materials. Wherever possible, suggestions are provided for the development of test techniques or phenomenological models which can be used for engineering applications. A methodology is proposed in the appendix to implement the findings of this thesis in real-world applications. Damage in the solder interconnect is quantified in terms of generic empirical metrics, PWA flexural strain and strain rate. It is shown that the proposed metrics (PWA strain and strain rate) can quantify the durability of the solder interconnect, irrespective of the loading orientation or the PWA boundary conditions