STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A 0.21-ps FOM Capacitor-Less Analog LDO with Dual-Range Load Current for Biomedical Applications

This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such as neural interfaces, IoT and edge devices with varying load currents. To enable rapid switching between low and high current states, a flipped voltage follower (FVF) configuration is utilized, along with a super source follower buffer to drive the power transistor. Two feedback loops and an on-chip compensation capacitor Cc maintain the stability of the regulator under various load conditions. The LDO was implemented in a 65nm CMOS process with 1.5V input and 1.2V output voltages. The measured quiescent current is as low as 3uA and 50uA for the 0-500uA and 5-15mA load current ranges, respectively. An undershoot voltage of 100mV is observed when the load current switches from 0 to 15mA within 80ns, with a maximum current efficiency of 99.98%. Our design achieved a low Figure-of-Merit of 0.21ps, outperforming state-of-the-art analog LDOs

Design of low-dropout regulator for ultra low power on-chip applications

Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

Modularizing the LDO to optimize performance based on application design constraints

This thesis aims to construct a modular low-dropout regulator that gives designers more freedom in building a highly efficient regulator that meets application demands. This modular design is able to separate DC regulation and high-frequency supply rejection while not compromising on either of the two. Flexibility is a key requirement during both design and post-design. The proposed regulator is able to achieve all the required goals with full spectrum power supply rejection. By splitting the pass device, this design is able to achieve the best of both internal pole dominant and external pole dominant linear regulators

A high-speed low-dropout voltage regulator using a compact output driver

Orientadores: Elnatan Chagas Ferreira, Sandro Augusto Pavlik HaddadTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Ao longo dos anos, microcontroladores tornaram-se mais rápidos e mais poderosos em sua capacidade de processamento graças à evolução dos processos de fabricação. Os novos processos CMOS de menores geometrias exigem tolerâncias menores quanto à tensão de ali-mentação. A lógica digital nesses dispositivos exige que o regulador interno forneça uma ten-são de alimentação estável e precisa, muitas vezes sem o auxílio de um capacitor externo de desacoplamento, o que torna o projeto do regulador uma tarefa árdua devido à natureza da carga digital. São milhões de portas lógicas comutando simultaneamente que ocasionam picos de corrente que podem atingir dezenas de vezes o valor médio do consumo de corrente. Como resultado, o regulador interno deve ser projetado para atender a esse perfil de carga, especial-mente durante as transições de modos de operação. Em outras palavras, quando o microcon-trolador sai de um modo de ultrabaixo consumo (de poucos microampères) para outro modo de operação de alto consumo de potência (dezenas ou centenas de miliampères) e vice-versa. Esse trabalho apresenta a implementação de um regulador LDO (low dropout) utilizan-do um dispositivo de saída NMOS que não sofre de problemas de estabilidade em altas fre-quências. A nova topologia alcança redução de área de silício significativa no estágio de saída e resposta transitória muito rápida para transições agressivas de carga, sem a necessidade de capacitor externo. Um protótipo do circuito proposto foi implementado em tecnologia CMOS split gate TFS (Thin Film Storage) de 90 nm. O silício foi encapsulado em QFP64 e avaliado em labora-tório nas dependências da NXP Semiconductors Brasil. Outra versão do circuito, em processo CMOS 55 nm, já está em produção, foi caracterizado e qualificado em ambiente automotivo. As medidas em laboratório demonstraram que o novo circuito responde extremamente rápido aos transientes de carga na versão fabricada em tecnologia CMOS 90 nm. Isso o torna apropri-ado para aplicações em microcontroladores (cargas predominantemente digitais). Na versão fabricada em 55 nm, mais de uma centena de peças foram medidas em pro-cesso (split lots) e temperatura e serviram para demonstrar que o circuito pode ser projetado também para aplicações focando baixo consumo energiaAbstract: Modern power management System-on-a-Chip (SoC) design demands for fully integrat-ed solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing the regulator response during aggressive load variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends. On-chip embedded LDO voltage regulators have to deliver stable and accurate local supply voltages to digital circuits that draw large and fast slew-rate current peaks, characteris-tics that are difficult to implement when off-chip inductors and capacitors are not used. The structure and frequency compensation scheme of classical LDO regulators, especially with low-voltage designs, present a trade-off between stability and transient response of the LDO regulator. To improve load regulation under large and fast load variations in linear regulators, it is necessary to employ large area output drivers. Thus, besides stability issues, another diffi-culty in designing LDOs is to create a compact driver with good load regulation and a fast transient response under large load variations. This manuscript presents a novel topology of a capacitor-free CMOS LDO regulator utilizing a compact NMOS output driver. The new output driver cell achieves low voltage ripple and very fast transient response under large load steps with a small silicone area. The circuit has been implemented in a 90 nm CMOS process technology. Silicon results demonstrated a transient loop response faster than 30 ns to a load variation of four orders of magnitude. Another version of the circuit has been implemented in a 55 nm CMOS technology. Alt-hough primarily targeted to attain low power requirements, this version has been qualified to meet industry standard automotive specifications and is currently in production as part of the Power Management Controller (PMC) block integrated within a family of MCUs used in au-tomotive and industrial powertrainDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétric

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

Recent advances in the hardware architecture of flat display devices

Thesis (Master)--Izmir Institute of Technology, Electronics and Communication Engineering, Izmir, 2007Includes bibliographical References (leaves: 115-117)Text in English; Abstract: Turkish and Englishxiii, 133 leavesThesis will describe processing board hardware design for flat panel displays with integrated digital reception, the design challenges in flat panel displays with integrated digital reception explained with details. Thesis also includes brief explanation of flat panel technology and processing blocks. Explanations of building blocks of TV and flat panel displays are given before design stage for better understanding of design stage. Hardware design stage of processing board is investigated in two major steps, schematic design and layout design. First step of the schematic design is system level block diagram design. Schematic diagram is the detailed application level hardware design and layout is the implementation level of the design. System level, application level and implementation level hardware design of the TV processing board is described with details in thesis. Design challenges, considerations and solutions are defined in advance for flat panel displays