Everything You Wish to Know About Memristors But Are Afraid to Ask

This paper classifies all memristors into three classes called Ideal, Generic, or Extended memristors. A subclass of Generic memristors is related to Ideal memristors via a one-to-one mathematical transformation, and is hence called Ideal Generic memristors. The concept of non-volatile memories is defined and clarified with illustrations. Several fundamental new concepts, including Continuum-memory memristor, POP (acronym for Power-Off Plot), DC V-I Plot, and Quasi DC V-I Plot, are rigorously defined and clarified with colorful illustrations. Among many colorful pictures the shoelace DC V-I Plot stands out as both stunning and illustrative. Even more impressive is that this bizarre shoelace plot has an exact analytical representation via 2 explicit functions of the state variable, derived by a novel parametric approach invented by the author

Lagrange formalism of memory circuit elements: classical and quantum formulations

The general Lagrange-Euler formalism for the three memory circuit elements, namely, memristive, memcapacitive, and meminductive systems, is introduced. In addition, {\it mutual meminductance}, i.e. mutual inductance with a state depending on the past evolution of the system, is defined. The Lagrange-Euler formalism for a general circuit network, the related work-energy theorem, and the generalized Joule's first law are also obtained. Examples of this formalism applied to specific circuits are provided, and the corresponding Hamiltonian and its quantization for the case of non-dissipative elements are discussed. The notion of {\it memory quanta}, the quantum excitations of the memory degrees of freedom, is presented. Specific examples are used to show that the coupling between these quanta and the well-known charge quanta can lead to a splitting of degenerate levels and to other experimentally observable quantum effects

Spontaneous bursting spike patterns seen in simple three memristor circuits

The distinctive switching spikes seen in single memristors are suppressed in networks of memristors. Instead oscillatory behaviour interrrupted by spontaneous irregular bursting spike patterns are seen. An investigation of two and three memrisor circuits was undertaken to elucidate the origin of these rich dynamics. No spiking is seen in circuits where all the memristors face the same way. Spiking is seen in circuits where memristors are arranged anti-parallel. These dynamics may be due to chaos and are potentially useful for neuromorphic computing

Teaching Memory Circuit Elements via Experiment-Based Learning

The class of memory circuit elements which comprises memristive, memcapacitive, and meminductive systems, is gaining considerable attention in a broad range of disciplines. This is due to the enormous flexibility these elements provide in solving diverse problems in analog/neuromorphic and digital/quantum computation; the possibility to use them in an integrated computing-memory paradigm, massively-parallel solution of different optimization problems, learning, neural networks, etc. The time is therefore ripe to introduce these elements to the next generation of physicists and engineers with appropriate teaching tools that can be easily implemented in undergraduate teaching laboratories. In this paper, we suggest the use of easy-to-build emulators to provide a hands-on experience for the students to learn the fundamental properties and realize several applications of these memelements. We provide explicit examples of problems that could be tackled with these emulators that range in difficulty from the demonstration of the basic properties of memristive, memcapacitive, and meminductive systems to logic/computation and cross-bar memory. The emulators can be built from off-the-shelf components, with a total cost of a few tens of dollars, thus providing a relatively inexpensive platform for the implementation of these exercises in the classroom. We anticipate that this experiment-based learning can be easily adopted and expanded by the instructors with many more case studies.Comment: IEEE Circuits and Systems Magazine (in press

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

A PUF based Lightweight Hardware Security Architecture for IoT

With an increasing number of hand-held electronics, gadgets, and other smart devices, data is present in a large number of platforms, thereby increasing the risk of security, privacy, and safety breach than ever before. Due to the extreme lightweight nature of these devices, commonly referred to as IoT or `Internet of Things\u27, providing any kind of security is prohibitive due to high overhead associated with any traditional and mathematically robust cryptographic techniques. Therefore, researchers have searched for alternative intuitive solutions for such devices. Hardware security, unlike traditional cryptography, can provide unique device-specific security solutions with little overhead, address vulnerability in hardware and, therefore, are attractive in this domain. As Moore\u27s law is almost at its end, different emerging devices are being explored more by researchers as they present opportunities to build better application-specific devices along with their challenges compared to CMOS technology. In this work, we have proposed emerging nanotechnology-based hardware security as a security solution for resource constrained IoT domain. Specifically, we have built two hardware security primitives i.e. physical unclonable function (PUF) and true random number generator (TRNG) and used these components as part of a security protocol proposed in this work as well. Both PUF and TRNG are built from metal-oxide memristors, an emerging nanoscale device and are generally lightweight compared to their CMOS counterparts in terms of area, power, and delay. Design challenges associated with designing these hardware security primitives and with memristive devices are properly addressed. Finally, a complete security protocol is proposed where all of these different pieces come together to provide a practical, robust, and device-specific security for resource-limited IoT systems

The Josephson junction as a quantum engine

We treat the Cooper pairs in the superconducting electrodes of a Josephson junction (JJ) as an open system, coupled via Andreev scattering to external baths of electrons. The disequilibrium between the baths generates the direct-current bias applied to the JJ. In the weak-coupling limit we obtain a Markovian master equation that provides a simple dynamical description consistent with the main features of the JJ, including the form of the current-voltage characteristic, its hysteresis, and the appearance under periodic voltage driving of discrete Shapiro steps. For small dissipation, our model also exhibits a self-oscillation of the JJ's electrical dipole with frequency $\Omega = 2 e V / \hbar$ around mean voltage $V$. This self-oscillation, associated with "hidden attractors" of the nonlinear equations of motion, explains the observed production of monochromatic radiation with frequency $\Omega$ and its harmonics. We argue that this picture of the JJ as a quantum engine resolves open questions about the Josephson effect as an irreversible process and could open new perspectives in quantum thermodynamics and in the theory of dynamical systems.Comment: 27 pages, 9 figures. v2: references added. v3: more references added, several points clarified, discussion of superradiance dynamics in Sec. VI A improved and factor of 2 corrected. v4: typos fixed and other minor improvements. To appear in New Journal of Physic

A superconducting nanowire spiking element for neural networks

As the limits of traditional von Neumann computing come into view, the brain's ability to communicate vast quantities of information using low-power spikes has become an increasing source of inspiration for alternative architectures. Key to the success of these largescale neural networks is a power-efficient spiking element that is scalable and easily interfaced with traditional control electronics. In this work, we present a spiking element fabricated from superconducting nanowires that has pulse energies on the order of ~10 aJ. We demonstrate that the device reproduces essential characteristics of biological neurons, such as a refractory period and a firing threshold. Through simulations using experimentally measured device parameters, we show how nanowire-based networks may be used for inference in image recognition, and that the probabilistic nature of nanowire switching may be exploited for modeling biological processes and for applications that rely on stochasticity.Comment: 5 main figures; 7 supplemental figure