Semiconductor Memory Applications in Radiation Environment, Hardware Security and Machine Learning System

abstract: Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications. In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level. Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well. Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm. Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

In-memory computing with emerging memory devices: Status and outlook

Supporting data for "In-memory computing with emerging memory devices: status and outlook", submitted to APL Machine Learning

Stochastic Memory Devices for Security and Computing

With the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles

Hybrid Memristor-CMOS Computer for Artificial Intelligence: from Devices to Systems

Neuromorphic computing systems, which aim to mimic the function and structure of the human brain, is a promising approach to overcome the limitations of conventional computing systems such as the von-Neumann bottleneck. Recently, memristors and memristor crossbars have been extensively studied for neuromorphic system implementations due to the ability of memristor devices to emulate biological synapses, thus providing benefits such as co-located memory/logic operations and massive parallelism. A memristor is a two-terminal device whose resistance is modulated by the history of external stimulation. The principle of the resistance modulation, or resistance switching, for a typical oxide-based memristor, is based on oxygen vacancy migration in the oxide layer through ion drift and diffusion. When applied in computing systems, the memristor is often formed in a crossbar structure and used to perform vector-matrix multiplication operations. Since the values in the matrix can be stored as the device conductance values of the crossbar array, when an input vector is applied as voltage pulses with different pulse amplitudes or different pulse widths to the rows of the crossbar, the currents or charges collected at the columns of the crossbar correspond to the resulting VMM outputs, following Ohm’s law and Kirchhoff’s current law. This approach makes it possible to use physics to execute direct computing of this data-intensive task, both in-memory and in parallel in a single step. First of all, I will present a comprehensive physical model of the TaOx-based memristor device where the internal parameters including electric field, temperature, and VO concentration are self-consistently solved to accurately describe the device operation. Starting from the initial Forming process, the model quantitatively captures the dynamic RS behavior, and can reliably reproduce Set/Reset cycling in a self-consistent manner. Beyond clarifying the nature of the Forming and Set/Reset processes, a bulk-like doping effect was revealed by the model during Set and supported by experimental results. This phenomenon can lead to linear analog conductance modulation with a large dynamic range, which is very beneficial for low-power neuromorphic computing applications. Second, an integrated memristor/CMOS system consisting of a 54×108 passive memristor crossbar array directly fabricated on a CMOS chip is presented. The system includes all necessary analog/digital circuitry (including analog-digital converters and digital-analog converters), digital buses, and a programmable processor to control the digital and analog components to form a complete hardware system for neuromorphic computing applications. With the fully-integrated and reprogrammable chip, we experimentally demonstrated three popular models – a perceptron network, a sparse coding network, and a bilayer principal component analysis system with an unsupervised feature extraction layer and a supervised classification layer – all on the same chip. Beyond VMM operations, the internal dynamics of memristors allow the system to natively process temporal features in the input data. Specifically, a WOx-based memristor with short-term memory effect caused by spontaneous oxygen vacancy diffusion was utilized to implement a reservoir computing system to process temporal information. The spatial information of a digit image can be converted into streaming inputs fed into the memristor reservoir, leading to 100% accuracy for simple 4×5 digit recognition and 88.1% accuracy for the MNIST data set. The system was also employed for solving other nonlinear tasks such as emulating a second-order nonlinear system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/155040/1/seulee_1.pd

Tailored electrical characteristics in multilayer metal-oxide-based-memristive devices

Auf Mehrlagen-Metalloxiden basierende memristive Bauelemente sind einer der vielversprechendsten Kandidaten für neuromorphes Computing. Allerdings stellen spezifische Anwendungen des neuromorphen Computings unterschiedliche Anforderungen an die memristiven Bauelemente. Eine ungelöste Herausforderung in der technologischen Entwicklung ist daher das maßgeschneiderte Design von memristiven Bauelementen für spezifische Anwendungen. Insbesondere die unterschiedlichen Materialien des Schichtstapels erschweren die Herstellungsprozesse aufgrund einer großen Anzahl von Parametern, wie z. B. der Stapelsequenzen und -dicken und der Qualität sowie der Eigenschaften der einzelnen Schichten. Daher sind systematische Untersuchungen der einzelnen Bauelementparameter besonders entscheidend. Darüber hinaus müssen sie mit einem tiefgreifenden Verständnis der zugrundeliegenden physikalischen Prozesse kombiniert werden, um die Lücke zwischen Materialdesign und elektrischen Eigenschaften der resultierenden memristiven Bauelemente zuschließen. Um memristive Bauelemente mit unterschiedlichen resistiven Schalteigenschaften zu erhalten, werden verschiedene Abfolgen und Kombinationen von drei Metalloxidschichten (TiOx, HfOx, und AlOx) hergestellt und untersucht. Zunächst werden einschichtige Oxidbauelemente untersucht, um Kandidaten für mehrschichtige Stapel zu identifizieren. Zweitens werden zweischichtige TiOx/HfOx Oxidbauelemente hergestellt. Anhand von systematischen Experimenten und statistischen Analysen wird gezeigt, dass die Stöchiometrie, die Dicke, und die Fläche des Bauelements die Betriebsspannungen, die Nichtlinearität beim resistiven Schalten und die Variabilität beeinflussen. Drittens werden TiOx/AlOx/HfOx-basierte Bauelemente hergestellt. Durch das Hinzufügen von AlOx in die zweischichtigen Oxidstapel weisen diese dreischichtigen Bauelemente optimale elektrische Eigenschaften für den Einsatz in neuromorpher Hardware auf, wie z. B. elektroformierungsfreies und strombegrenzungsloses Schalten sowie eine lange Lebensdauer. Die entwickelten memristiven Bauelemente werden in Systeme, wie Kreuzpunkt-Strukturen und Ein-Transistor-ein-Memristor-Konfigurationen integriert. Hier wird die Eignung für effizientes neuromorphes Computing bewertet. Außerdem werden Methoden zur stufenlosen analogen Einstellung des Widerstands der Bauelemente demonstriert. Diese Eigenschaft ermöglicht effiziente neuromorphe Rechenschemata. Diese umfassende Studie beleuchtet die Beziehung zwischen den Bauelementparametern und den elektrischen Eigenschaften von mehrschichtigen memristiven Bauelementen auf Metalloxidbasis. Auf dieser Grundlage werden maßgeschneiderte Methoden für spezifische neuromorphe Anwendungen entwickelt.Multilayer metal-oxide-based-memristive devices are one of the most promising candidates for neuromorphic computing. However, specific applications of neuromorphic computing call for different requirements for memristive devices. Therefore, an open challenge in technological development is the tailored design of memristive devices for specific applications. In particular, multilayer stacks complicate fabrication processes due to a large number of device parameters such as staking sequences and thicknesses, quality, and property of each layer. Therefore, systematic investigations of the individual device parameters are particularly decisive. Moreover, they need to be combined with a profound understanding of the underlying physical processes to bridge the gap between material design and electrical characteristics of the resulting memristive devices. To obtain memristive devices with different resistance switching characteristics, various sequences and combinations of three metal oxide layers (TiOx, HfOx, and AlOx) are fabricated and studied. First, single-layer oxide devices are investigated to find desirable multilayer stacks for memristive devices. Second, TiOx/HfOx-based bilayer oxide devices are fabricated. Via systematic experiments and statistical analysis, it is shown that the stoichiometry, thickness, and device area influence operating voltages, non-linearity in resistive switching, and variability. Third, TiOx/AlOx/HfOx-based devices are fabricated. By adding AlOx into the bilayer oxide stacks, these trilayer devices present favorable electrical features for use in neuromorphic hardware, such as electroforming-free and compliance-free switching as well as long retention. The developed memristive devices are integrated into systems such as crossbar structures and one-transistor-one-memristor configurations. Here, suitability for efficient neuromorphic computing is assessed. Also, methods to tune the device resistance gradually in an analog fashion are demonstrated. This feature allows for efficient neuromorphic computation. This comprehensive study highlights the relationship between device parameters and electrical properties of multilayer metal-oxide-based memristive devices. On this basis, tailoring methodologies are established for specific neuromorphic applications

Cerium oxide based resistive random access memory devices

Resistive Random Access Memory (RRAM) is an emerging technology of non-volatile memory (NVM). Although the observation of metal oxide that can undergo an abrupt insulator-metal transition into a conductive state has been known for over 40 years, researchers started investigating those materials for memory applications in late 1990s. It has been considered as the next generation memory technology to replace current flash memory because RRAM has demonstrated feasible switching characteristics and potential to build high density arrays and also RRAM is also compatible with contemporary CMOS processes, which means RRAM can be integrated into current CMOS chips. While the structure of RRAM is a simple metal-insulator-metal (MIM) device, there are numerous materials that exhibit resistive switching. The switching behavior is not only dependent on the switching layer materials but also dependent on the choice of metal electrodes and their interfacial properties. Many metal oxides such as hafnium oxide, titanium oxide, aluminum oxide, nickel oxide (NiO), tantalum oxide and etc. have been studied in details; however, some materials are unexplored such as cerium oxide. In addition to nonvolatile storage applications, RRAM is considered as one of essential elements for advancing neuromorphic computing because of its analog switching and retention characteristics. This thesis investigated CeO[subscript x]-based RRAMs, from its fundamental device characteristics to neuromorphic applications.Electrical and Computer Engineerin

Nano-intrinsic security primitives for internet of everything

With the advent of Internet-enabled electronic devices and mobile computer systems, maintaining data security is one of the most important challenges in modern civilization. The innovation of physically unclonable functions (PUFs) shows great potential for enabling low-cost low-power authentication, anti-counterfeiting and beyond on the semiconductor chips. This is because secrets in a PUF are hidden in the randomness of the physical properties of desirably identical devices, making it extremely difficult, if not impossible, to extract them. Hence, the basic idea of PUF is to take advantage of inevitable non-idealities in the physical domain to create a system that can provide an innovative way to secure device identities, sensitive information, and their communications. While the physical variation exists everywhere, various materials, systems, and technologies have been considered as the source of unpredictable physical device variation in large scales for generating security primitives. The purpose of this project is to develop emerging solid-state memory-based security primitives and examine their robustness as well as feasibility. Firstly, the author gives an extensive overview of PUFs. The rationality, classification, and application of PUF are discussed. To objectively compare the quality of PUFs, the author formulates important PUF properties and evaluation metrics. By reviewing previously proposed constructions ranging from conventional standard complementary metal-oxide-semiconductor (CMOS) components to emerging non-volatile memories, the quality of different PUFs classes are discussed and summarized. Through a comparative analysis, emerging non-volatile redox-based resistor memories (ReRAMs) have shown the potential as promising candidates for the next generation of low-cost, low-power, compact in size, and secure PUF. Next, the author presents novel approaches to build a PUF by utilizing concatenated two layers of ReRAM crossbar arrays. Upon concatenate two layers, the nonlinear structure is introduced, and this results in the improved uniformity and the avalanche characteristic of the proposed PUF. A group of cell readout method is employed, and it supports a massive pool of challenge-response pairs of the nonlinear ReRAM-based PUF. The non-linear PUF construction is experimentally assessed using the evaluation metrics, and the quality of randomness is verified using predictive analysis. Last but not least, random telegraph noise (RTN) is studied as a source of entropy for a true random number generation (TRNG). RTN is usually considered a disadvantageous feature in the conventional CMOS designs. However, in combination with appropriate readout scheme, RTN in ReRAM can be used as a novel technique to generate quality random numbers. The proposed differential readout-based design can maintain the quality of output by reducing the effect of the undesired noise from the whole system, while the controlling difficulty of the conventional readout method can be significantly reduced. This is advantageous as the differential readout circuit can embrace the resistance variation features of ReRAMs without extensive pre-calibration. The study in this thesis has the potential to enable the development of cost-efficient and lightweight security primitives that can be integrated into modern computer mobile systems and devices for providing a high level of security

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within