Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

NASA Tech Briefs, October 2013

Topics include: A Short-Range Distance Sensor with Exceptional Linearity; Miniature Trace Gas Detector Based on Microfabricated Optical Resonators; Commercial Non-Dispersive Infrared Spectroscopy Sensors for Sub-Ambient Carbon Dioxide Detection; Fast, Large-Area, Wide-Bandgap UV Photodetector for Cherenkov Light Detection; Mission Data System Java Edition Version 7; Adaptive Distributed Environment for Procedure Training (ADEPT); LEGEND, a LEO-to-GEO Environment Debris Model; Electronics/Computers; Millimeter-Wave Localizers for Aircraft-to-Aircraft Approach Navigation; Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces; SpaceCube Version 1.5; High-Pressure Lightweight Thrusters; Non-Magnetic, Tough, Corrosion- and Wear-Resistant Knives From Bulk Metallic Glasses and Composites; Ambient Dried Aerogels; Applications for Gradient Metal Alloys Fabricated Using Additive Manufacturing; Passivation of Flexible YBCO Superconducting Current Lead With Amorphous SiO2 Layer; Propellant-Flow-Actuated Rocket Engine Igniter; Lightweight Liquid Helium Dewar for High-Altitude Balloon Payloads; Method to Increase Performance of Foil Bearings Through Passive Thermal Management; Unibody Composite Pressurized Structure; JWST Integrated Science Instrument Module Alignment Optimization Tool; Radar Range Sidelobe Reduction Using Adaptive Pulse Compression Technique; Digitally Calibrated TR Modules Enabling Real-Time Beamforming SweepSAR Architectures; Electro-Optic Time-to-Space Converter for Optical Detector Jitter Mitigation; Partially Transparent Petaled Mask/Occulter for Visible-Range Spectrum; Educational NASA Computational and Scientific Studies (enCOMPASS); Coarse-Grain Bandwidth Estimation Scheme for Large-Scale Network; Detection of Moving Targets Using Soliton Resonance Effect; High-Efficiency Nested Hall Thrusters for Robotic Solar System Exploration; High-Voltage Clock Driver for Photon-Counting CCD Characterization; Development of the Code RITRACKS; and Enabling Microliquid Chromatography by Microbead Packing of Microchannels

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Efficient Design Techniques of Switches for Optical Networks and Data Centers

Η σύγχρονη σχεδίαση των Κέντρων Δεδομένων εκμεταλλεύεται τις δυνατότητες που προσφέρει η οπτική μεταγωγή με στόχο την διασύνδεση των μεταγωγών ικριώματος μεταξύ τους, οι οποίοι εξυπηρετούν χιλιάδες συσκευές αποθήκευσης και υπολογιστικά συστήματα. Οι καινοτομίες στον τομέα τον οπτικών επικοινωνιών και της οπτικής μεταγωγής συνέβαλλαν σημαντικά στην ανάπτυξη των Κέντρων Δεδομένων με υψηλής διεκπεραιωτικότητας δίκτυα διασύνδεσης. Σημαντική συνεισφορά στα προηγμένα οπτικά Κέντρα Δεδομένων παρουσιάζει η αρχιτεκτονική Nephele, η οποία χρησιμοποιεί οπτικά επίπεδα δεδομένων, οπτικούς μεταγωγούς στα Σημεία Παράδοσης και μεταγωγούς Ικριώματος με δυνατότητα διασύνδεσης της τάξης των 10 Gpbs μεταξύ των Σημείων Παράδοσης και των εξυπηρετητών. Η αρχιτεκτονική Nephele ακολουθεί την Δικτύωση Βασισμένη σε Λογισμικό, χρησιμοποιεί το πρωτόκολλο OpenFlow και στηρίζεται σε έναν Πράκτορα Λογισμικού, ο οποίος υλοποιεί την μεταφορά των εντολών του πρωτοκόλλου στους μεταγωγούς του επιπέδου δεδομένων. ΄Ενας μεταγωγός Ικριώματος καλείται συνήθως να υποστηρίζει την λειτουργία των Εικονικών Ουρών Εξόδου, οι οποίες αποτελούν την επικρατέστερη λύση στο πρόβλημα του αποκλεισμού μετάδοσης πακέτων που προέρχονται από την ίδια είσοδο σε πολλαπλές εξόδους του μεταγωγού. Μία αποτελεσματική αρχιτεκτονική Εικονικών Ουρών Εξόδου βελτιώνει την επίδοση του Κέντρου Δεδομένων μειώνοντας την λανθάνουσα καθυστέρηση της επικοινωνίας πλαισίων δεδομένων και ειναι αποδοτική όσον αφορά το κόστος υλοποίησης. Η συγκεκριμένη διατριβή εισάγει μία αρχιτεκτονική Εικονικών Ουρών Εξόδου για μεταγωγούς Ικριώματος Κέντρων Δεδομένων τα οποία λειτουργούν σύμφωνα με την μέθοδο πολλαπλής πρόσβασης διαίρεσης χρόνου. Η προτεινόμενη αρχιτεκτονική Εικονικών Ουρών Εξόδου περιλαμβάνει έναν περιορισμένο αριθμό ουρών σε κάθε πόρτα εισόδου που υποστηρίζουν τους ενεργούς προορισμούς και αποθηκεύουν προσωρινά τα πακέτα Ethernet σε δυναμική μνήμη τυχαίας προσπέλασης. ΄Ενας αποδοτικός μηχανισμός χαμηλής λανθάνουσας καθυστέρησης αντιστοιχεί κάθε ουρά σε έναν ενεργό προορισμό. Οι Εικονικές Ουρές Εξόδου αποτελούν ένα δομικό στοιχείο του μεταγωγού Ικριώματος, ο οποίος βασίζεται σε ένα εμπορικά διαθέσιμο μεταγωγό Ethernet και σε δύο κάρτες Xilinx FPGA , την Virtex VC707 και την NetFPGA. Η αρχιτεκτονική των Εικονικών Ουρών Εξόδου υλοποιήθηκε και επαληθεύτηκε μέσω δοκιμών στην κάρτα NetFPGA. Επιπλέον, η συγκεκριμένη διατριβή παρουσιάζει ένα εργαλείο διαχείρισης για τον Πράκτορα Λογισμικού του Κέντρου Δεδομένων. Η Γραφική Διεπαφή Χρήστη του εργαλείου διαχείρισης του Πράκτορα Λογισμικού χρησιμοποιείται για την διαμόρφωση του Πράκτορα Λογισμικού, την δημιουργία εντολών, την εκτέλεση λειτουργιών σε βήματα και την παρακολούθηση των αποτελεσμάτων και της κατάστασης των μεταγωγών. Χρησιμοποιούμενο ως εργαλείο δοκιμών και επαλήθευσης, διαδραματίζει ένα σημαντικό ρόλο στην βελτίωση της σχεδίασης του Πράκτορα Λογισμικού καθώς επίσης και στην αναβάθμιση ολόκληρης της οργάνωσης του Κέντρου Δεδομένων και των επιδόσεων του. Επιπρόσθετα, με στόχο την Διασφάλιση της Ποιότητας Υπηρεσιών για τις ποικίλες εφαρμογές των Κέντρων Δεδομένων πρόσφατες έρευνες αξιοποιούν σύγχρονες τεχνικές Βαθιάς Μάθησης. Η πληθώρα από εφαρμογές Μηχανικής και Βαθιάς Μάθησης περιλαμβάνουν πολύπλοκες διεργασίες που επιβάλλουν την ανάγκη των Επιταχυντών Υλικού για την εκτέλεσή τους σε πραγματικό χρόνο. Μεταξύ αυτόν, αξιοσημείωτα είναι τα Συνελικτικά Νευρωνικά Δίκτυα για εφαρμογές κατηγοριοποίησης. Με στόχο την συνεισφορά στον τομέα των Επιταχυντών Υλικού Συνελικτικών Νευρωνικών Δικτύων, η παρούσα διατριβή επικεντρώνεται σε νευρωνικά δίκτυα περιορισμένου αριθμού χαρακτηριστικών για να βελτιώσει τις επιδόσεις, την κατανάλωση ενέργειας και την αξιοποίηση των πόρων, στοιχεία που τελικά θα δώσουν την δυνατότητα για την χρήση τους τοπικά στους μεταγωγούς ενός Κέντρου Δεδομένων. Η προτεινόμενη σχεδιαστική προσέγγιση Συνελικτικών Νευρωνικών Δικτύων στοχεύει στην αξιοποίηση των πόρων λογικής και μνήμης ενός FPGA, και ωφελεί πολυάριθμες εφαρμογές όπως Αποκεντρωμένες και Φορητές εφαρμογές, Κέντρα Δεδομένων και Δορυφορικές εφαρμογές. Η συγκεκριμένη διατριβή εκμεταλλεύεται την προτεινόμενη σχεδιαστική προσέγγιση, ώστε να αναπτύξει ένα Παράδειγμα Επιταχυντή για Αναγνώριση Πλοίων, στην κάρτα Xilinx Virtex 7 XC7VX485T FPGA.Η παραχθείσα αρχιτεκτονική επιτυγχάνει συχνότητα λειτουργίας 270 MHz , καταναλώνοντας 5 watt επαληθεύοντας την σχεδιαστική προσέγγιση.The latest design approach for Data Centers follows the direction of exploiting optical switching to interconnect Top-of-Rack (ToR) switches that serve thousands of data storing and computing devices. Optical switching provided the means for the development of Data Centers with high throughput interconnection networks. A significant contribution to the advanced optical Data Centers designs is the Nephele architecture that employs optical data planes, optical Points of Delivery (PoD) switches and ToR switches equipped with 10 Gbps connections to the PoDs and the servers. Nephele follows the Software Defined Network (SDN) paradigm based on the OpenFlow protocol and it employs an Agent communicating the protocol commands to the data plane. A ToR’s usual function is the Virtual Output Queues (VOQs), which is the prevalent solution for the head-of-line blocking problem of the Data Center switches. An effective VOQs architecture improves the Data Center’s performance by reducing the frames communication latency and it is efficient with respect to the implementation cost. The current thesis introduces a VOQs architecture for the Data Center’s ToR switches that function with Time Division Multiple Access (TDMA). The proposed VOQs architecture contains a bounded number of queues at each input port supporting the active destinations and forwarding the input Ethernet frames to a shared memory buffer. An efficient mechanism of low latency grants each queue to an active destination. The VOQs constitutes a module of a ToR development, which is based on a commercially available Ethernet switch and two FPGA Xilinx boards, the Virtex VC707 and the Xilinx NetFPGA. The VOQs architecture’s implementation and validation took place on the NetFPGA board. Moreover, the current thesis presents a management tool for the control plane’s Agent of the Data Center. The Graphical User Interface (GUI) of the Agent’s management tool is utilized to configure the Agent, create commands, perform step operations and monitor the results and the status. When used as a testing and validation tool, it plays a significant role in the improvement of the Agent’s design as well as in the upgrade of the entire Data Center’s organization and performance. Furthermore, aiming to improve the Quality of Service (QoS) for diverse applications of the Data Center, recent works utilize advanced Deep Learning techniques. The plethora of Machine and Deep Learning applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable are the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) for classification applications.Aiming at contributing to the CNN accelerator solutions, the current thesis focuses on the design of FPGA Accelerators for CNNs of limited feature space to improve performance, power consumption and resource utilization, merits that ultimately enable the use of CNNs locally at the Data Center’s ToR switches. The proposed CNN design approach targets the designs that can utilize the logic and memory resources of a single FPGA device and benefit numerous applications like the Edge, Mobile, Data Center and On-board satellite (OBC) Computing. This work exploits the proposed approach to develop an Example FPGA Accelerator for Vessel Detection, on a Xilinx Virtex 7 XC7VX485T FPGA device. The resulting architecture achieves an operating frequency of 270 MHz, while consuming 5 watts, it validates the approach

Distributed computing in space-based wireless sensor networks

This thesis investigates the application of distributed computing in general and wireless sensor networks in particular to space applications. Particularly, the thesis addresses issues related to the design of "space-based wireless sensor networks" that consist of ultra-small satellite nodes flying together in close formations. The design space of space-based wireless sensor networks is explored. Consequently, a methodology for designing space-based wireless sensor networks is proposed that is based on a modular architecture. The hardware modules take the form of 3-D Multi-Chip Modules (MCM). The design of hardware modules is demonstrated by designing a representative on-board computer module. The onboard computer module contains an FPGA which includes a system-on-chip architecture that is based on soft components and provides a degree of flexibility at the later stages of the design of the mission.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

NASA Tech Briefs, November 2012

The topics include: Visual System for Browsing, Analysis, and Retrieval of Data (ViSBARD); Time-Domain Terahertz Computed Axial Tomography NDE System; Adaptive Sampling of Time Series During Remote Exploration; A Tracking Sun Photometer Without Moving Parts; Surface Temperature Data Analysis; Modular, Autonomous Command and Data Handling Software with Built-In Simulation and Test; In-Situ Wire Damage Detection System; Amplifier Module for 260-GHz Band Using Quartz Waveguide Transitions; Wideband Agile Digital Microwave Radiometer; Buckyball Nucleation of HiPco Tubes; FACT, Mega-ROSA, SOLAROSA; An Integrated, Layered-Spinel Composite Cathode for Energy Storage Applications; Engineered Multifunctional Surfaces for Fluid Handling; Polyolefin-Based Aerogels; Adjusting Permittivity by Blending Varying Ratios of SWNTs; Gravity-Assist Mechanical Simulator for Outreach; Concept for Hydrogen-Impregnated Nanofiber/Photovoltaic Cargo Stowage System; DROP: Durable Reconnaissance and Observation Platform; Developing Physiologic Models for Emergency Medical Procedures Under Microgravity; Spectroscopic Chemical Analysis Methods and Apparatus; Low Average Sidelobe Slot Array Antennas for Radiometer Applications; Motion-Corrected 3D Sonic Anemometer for Tethersondes and Other Moving Platforms; Water Treatment Systems for Long Spaceflights; Microchip Non-Aqueous Capillary Electrophoresis (MicronNACE) Method to Analyze Long-Chain Primary Amines; Low-Cost Phased Array Antenna for Sounding Rockets, Missiles, and Expendable Launch Vehicles; Mars Science Laboratory Engineering Cameras; Seismic Imager Space Telescope; Estimating Sea Surface Salinity and Wind Using Combined Passive and Active L-Band Microwave Observations; A Posteriori Study of a DNS Database Describing Super critical Binary-Species Mixing; Scalable SCPPM Decoder; QuakeSim 2.0; HURON (HUman and Robotic Optimization Network) Multi-Agent Temporal Activity Planner/Scheduler; MPST Software: MoonKomman

A novel parallel algorithm for surface editing and its FPGA implementation

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophySurface modelling and editing is one of important subjects in computer graphics. Decades of research in computer graphics has been carried out on both low-level, hardware-related algorithms and high-level, abstract software. Success of computer graphics has been seen in many application areas, such as multimedia, visualisation, virtual reality and the Internet. However, the hardware realisation of OpenGL architecture based on FPGA (field programmable gate array) is beyond the scope of most of computer graphics researches. It is an uncultivated research area where the OpenGL pipeline, from hardware through the whole embedded system (ES) up to applications, is implemented in an FPGA chip. This research proposes a hybrid approach to investigating both software and hardware methods. It aims at bridging the gap between methods of software and hardware, and enhancing the overall performance for computer graphics. It consists of four parts, the construction of an FPGA-based ES, Mesa-OpenGL implementation for FPGA-based ESs, parallel processing, and a novel algorithm for surface modelling and editing. The FPGA-based ES is built up. In addition to the Nios II soft processor and DDR SDRAM memory, it consists of the LCD display device, frame buffers, video pipeline, and algorithm-specified module to support the graphics processing. Since there is no implementation of OpenGL ES available for FPGA-based ESs, a specific OpenGL implementation based on Mesa is carried out. Because of the limited FPGA resources, the implementation adopts the fixed-point arithmetic, which can offer faster computing and lower storage than the floating point arithmetic, and the accuracy satisfying the needs of 3D rendering. Moreover, the implementation includes Bézier-spline curve and surface algorithms to support surface modelling and editing. The pipelined parallelism and co-processors are used to accelerate graphics processing in this research. These two parallelism methods extend the traditional computation parallelism in fine-grained parallel tasks in the FPGA-base ESs. The novel algorithm for surface modelling and editing, called Progressive and Mixing Algorithm (PAMA), is proposed and implemented on FPGA-based ES’s. Compared with two main surface editing methods, subdivision and deformation, the PAMA can eliminate the large storage requirement and computing cost of intermediated processes. With four independent shape parameters, the PAMA can be used to model and edit freely the shape of an open or closed surface that keeps globally the zero-order geometric continuity. The PAMA can be applied independently not only FPGA-based ESs but also other platforms. With the parallel processing, small size, and low costs of computing, storage and power, the FPGA-based ES provides an effective hybrid solution to surface modelling and editing

Fault Tolerant Cryptographic Primitives for Space Applications

Spacecrafts are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, there has been an increasing demand to utilize strong cryptographic primitives to assure their security. Moreover, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. The problem of recovering spacecrafts from failures or attacks, and bringing them back to an operational and safe state is crucial for reliability. Despite the recent interest in incorporating on-board security, there is limited research in this area. This research proposes a trusted hardware module approach for recovering the spacecrafts subsystems and their cryptographic capabilities after an attack or a major failure has happened. The proposed fault tolerant trusted modules are capable of performing platform restoration as well as recovering the cryptographic capabilities of the spacecraft. This research also proposes efficient fault tolerant architectures for the secure hash (SHA-2) and message authentication code (HMAC) algorithms. The proposed architectures are the first in the literature to detect and correct errors by using Hamming codes to protect the main registers. Furthermore, a quantitative analysis of the probability of failure of the proposed fault tolerance mechanisms is introduced. Based upon an extensive set of experimental results along with probability of failure analysis, it was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR). The fault tolerant cryptographic primitives introduced in this research are of crucial importance for the implementation of on-board security in spacecrafts

Design and implementation of an SDR-based multi-frequency ground-based SAR system

Synthetic Aperture Radar (SAR) has proven a valuable tool in the monitoring of the Earth, either at a global or local scales. SAR is a coherent radar system able to image extended areas with high resolution, and finds applications in many areas such as forestry, agriculture, mining, structure inspection or security operations. Although space-borne SAR systems can image extended areas, their main limitation is the long revisit times, which are not suitable for applications where the target experiments rapid changes, in the scale of minutes to few days. GBSAR systems have proven useful to fill this revisit time gap by imaging relatively small areas continuously, with extensions usually smaller than a few square kilometers. Ground Based SAR (GBSAR) systems have been used extensively for the monitoring of slope instability, and are a common tool in the mining sector. The development of the GBSAR is relatively recent, and various developments have taken place since the 2000s, transitioning from the usage of Vector Network Analyzers (VNAs) to custom radar cores tailored for this application. This transition is accompanied by a reduction in cost, but at the same time is accompanied by a loss of operational flexibility. Specifically, most GBSAR sensors now operate at a single frequency, losing the value of the multi-band operation that VNAs provided. This work is motivated by the idea that it is worth to use the value of multi-frequency GBSAR measurements, while maintaining a limited system cost. In order to implement a GBSAR with these characteristics, it is realized that Software Defined Radio (SDR) devices are a good option for fast and flexible implementation of broadband transceivers. This thesis details the design and implementation process of an SDR-based Frequency Modulated Continuous Wave (FMCW) GBSAR system from the ground up, presenting the main issues related with the usage of the most common SDR analog architecture, the Zero-IF transceiver. The main problem is determined to be the behavior of spurs related to IQ imbalances of the analog transceiver with the FMCW demodulation process. Two effective techniques to overcome these issues, the Super Spatial Variant Apodization (SSVA) and the Short Time Fourier Transform (STFT) signal reconstruction techniques, are implemented and tested. The thesis also deals with the digital implementation of the signal generator and digital receiver, which are implemented on top of an RF Network-on-Chip (RFNoC) architecture in the SDR Field Programmable Gate Array (FPGA). Another important aspect of this work is the development of an radiofrequency front-end that extends the capabilities of the SDR, implementing filtering, amplification, leakage mitigation and up-conversion to X-band. Finally, a set of test campaigns is described, in which the operation of the system is verified and the value of multi-frequency GBSAR observations is shown.El radar d'obertura sintètica (SAR) ha demostrat ser una eina valuosa en el monitoratge de la Terra, sigui a escala global o local. El SAR és un sistema de radar coherent capaç d’obtenir imatges de zones extenses amb alta resolució i té aplicacions en moltes àrees com la silvicultura, l’agricultura, la mineria, la inspecció d’estructures o les operacions de seguretat. Tot i que els sistemes SAR embarcats en plataformes orbitals poden obtenir imatges d'àrees extenses, la seva principal limitació és el temps de revisita, que no són adequats per a aplicacions on l'objectiu experimenta canvis ràpids, en una escala de minuts a pocs dies. Els sistemes GBSAR han demostrat ser útils per omplir aquesta bretxa de temps, obtenint imatges d'àrees relativament petites de manera contínua, amb extensions generalment inferiors a uns pocs quilòmetres quadrats. Els sistemes SAR terrestres (GBSAR) s’han utilitzat àmpliament per al control de la inestabilitat de talussos i esllavissades i són una eina comuna al sector miner. El desenvolupament del GBSAR és relativament recent i s’han produït diversos desenvolupaments des de la dècada de 2000, passant de l’ús d’analitzadors de xarxes vectorials (VNA) a nuclis de radar personalitzats i adaptats a aquesta aplicació. Aquesta transició s’acompanya d’una reducció del cost, però al mateix temps d’una pèrdua de flexibilitat operativa. Concretament, la majoria dels sensors GBSAR funcionen a una única freqüència, perdent el valor de l’operació en múltiples bandes que proporcionaven els VNA. Aquesta tesi està motivada per la idea de recuperar el valor de les mesures GBSAR multifreqüència, mantenint un cost del sistema limitat. Per tal d’implementar un GBSAR amb aquestes característiques, s’adona que els dispositius de ràdio definida per software (SDR) són una bona opció per a la implementació ràpida i flexible dels transceptors de banda ampla. Aquesta tesi detalla el procés de disseny i implementació d’un sistema GBSAR d’ona contínua modulada en freqüència (FMCW) basat en la tecnologia SDR, presentant els principals problemes relacionats amb l’ús de l’arquitectura analògica de SDR més comuna, el transceptor Zero-IF. Es determina que el problema principal és el comportament dels espuris relacionats amb el balanç de les cadenes de fase i quadratura del transceptor analògic amb el procés de desmodulació FMCW. S’implementen i comproven dues tècniques efectives per minimitzar aquests problemes basades en la reconstrucció de la senyal contaminada per espuris: la tècnica anomenada Super Spatial Variant Apodization (SSVA) i una tècnica basada en la transformada de Fourier amb finestra (STFT). La tesi també tracta la implementació digital del generador de senyal i del receptor digital, que s’implementen sobre una arquitectura RF Network-on-Chip (RFNoC). Un altre aspecte important d’aquesta tesi és el desenvolupament d’un front-end de radiofreqüència que amplia les capacitats de la SDR, implementant filtratge, amplificació, millora de l'aïllament entre transmissió i recepció i conversió a banda X. Finalment, es descriu un conjunt de campanyes de prova en què es verifica el funcionament del sistema i es mostra el valor de les observacions GBSAR multifreqüència