Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

Master'sMASTER OF ENGINEERIN

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Integrated 3D glass modules with high-Q inductors and thermal dissipation for RF front-end applications

The objectives of this research are to model, design, fabricate and validate high quality factor (Q > 100 at 2.4 GHz for 3-10 nH/mm2) inductors and innovative thermal structures with copper through-package vias to maintain low junction temperatures of < 85 oC in power amplifiers, and demonstrate ultra-thin fully-integrated dual-band (2.4 GHz/ 5GHz) WLAN modules with passive-active integration on ultra-thin glass substrates with double-side RF circuits and copper through-package vias (TPVs). Today’s RF subsystems are 2D single or multichip packages made of either organic laminates or LTCC (low temperature co-fired ceramic) substrates. The need for form-factor reduction in RF subsystems in both z and x-y direction has led to the evolution of embedded die-package architectures in thin laminates with dies facing up or down. This also reduces insertion loss and improves signal integrity by minimizing electromagnetic interference (EMI), package parasitics and routing issues. For further improvement in performance and miniaturization, glass is proposed as an ideal substrate for RF module integration. However, major design and fabrication challenges need to be addressed to achieve ultra-thin high Q RF components and also enable IC cooling to eliminate hotspots on glass substrates, which forms the key focus of this thesis.Ph.D

Analysis of column interconnects for wafer level packages

Master'sMASTER OF ENGINEERIN

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Development of effective thermal management strategies for LED luminaires

The efficacy, reliability and versatility of the light emitting diode (LED) can outcompete most established light source technologies. However, they are particularly sensitive to high temperatures, which compromises their efficacy and reliability, undermining some of the technology s key benefits. Consequently, effective thermal management is essential to exploit the technology to its full potential. Thermal management is a well-established subject but its application in the relatively new LED lighting industry, with its specific constraints, is currently poorly defined. The question this thesis aims to answer is how can LED thermal management be achieved most effectively? This thesis starts with a review of the current state of the art, relevant thermal management technologies and market trends. This establishes current and future thermal management constraints in a commercial context. Methods to test and evaluate the thermal management performance of a luminaire system follow. The defined test methods, simulation benchmarks and operational constraints provide the foundation to develop effective thermal management strategies. Finally this work explores how the findings can be implemented in the development and comparison of multiple thermal management designs. These are optimised to assess the potential performance enhancement available when applied to a typical commercial system. The outcomes of this research showed that thermal management of LEDs can be expected to remain a key requirement but there are hints it is becoming less critical. The impacts of some common operating environments were studied, but appeared to have no significant effect on the thermal behaviour of a typical system. There are some active thermal management devices that warrant further attention, but passive systems are inherently well suited to LED luminaires and are readily adopted so were selected as the focus of this research. Using the techniques discussed in this thesis the performance of a commercially available component was evaluated. By optimising its geometry, a 5 % decrease in absolute thermal resistance or a 20 % increase in average heat transfer coefficient and 10 % reduction in heatsink mass can potentially be achieved . While greater lifecycle energy consumption savings were offered by minimising heatsink thermal resistance the most effective design was considered to be one optimised for maximum average heat transfer coefficient. Some more radical concepts were also considered. While these demonstrate the feasibility of passively manipulating fluid flow they had a detrimental impact on performance. Further analysis would be needed to conclusively dismiss these concepts but this work indicates there is very little potential in pursuing them further

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Experimental Study of Novel Materials and Module for Cryogenic (4K) Superconducting Multi-Chip Modules

The objectives of this proposal are to understand the science and technology of interfaces in the packaging of superconducting electronic (SCE) multichip modules (MCMs) at 4 K. The thermal management issue of the current SCE-MCMs was examined and the package assembly was optimized. A novel thermally conducting and electrically insulating nano-engineered polymer was developed for the thermal management of SCE-MCMs for 4 K cryogenic packaging. Finally, the nano-engineered polymer was integrated as underfill in a SCE-MCM and the thermal and electrical performance of SCE-MCM was demonstrated at 4 K. Niobium based superconducting electronics (SCE) are the fastest known digital logic which operate at 100GHz and greater. Nevertheless, the performance of the SCE device depends on the temperature of the SCE integrated circuits being maintained between 4.2 - 4.25 K. Additionally, as semiconductors are slowly approaching their performance limitations the SCE devices are viewed as a viable alternative for high end computing and commercial wireless applications. However, the successful implementation of SCE\u27s requires the demonstration of these devices in multichip module (MCM) architecture. Thus the stringent thermal constraint and the complex MCM architecture require an innovative method for thermal management which is addressed by the current research