Proxy Blind Signature using Hyperelliptic Curve Cryptography

Blind signature is the concept to ensure anonymity of e-coins. Untracebility and unlinkability are two main properties of real coins and should also be mimicked electronically. A user has to fulll above two properties of blind signature for permission to spend an e-coin. During the last few years, asymmetric cryptosystems based on curve based cryptographiy have become very popular, especially for embedded applications. Elliptic curves(EC) are a special case of hyperelliptic curves (HEC). HEC operand size is only a fraction of the EC operand size. HEC cryptography needs a group order of size at least 2160. In particular, for a curve of genus two eld Fq with p 280 is needeed. Therefore, the eld arithmetic has to be performed using 80-bit long operands. Which is much better than the RSA using 1024 bit key length. The hyperelliptic curve is best suited for the resource constraint environments. It uses lesser key and provides more secure transmisstion of data

Implementación de aritmética de torres de campos finitos binarios de extensión 2 en FPGA

En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m), extendidos usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad; se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 14.4

Implementation of tower of finite field arithmetics in binary quadratic forms for fpga

En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m), extendidos usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad; se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 14.4This work shows the basics of the arithmetic of binary finite fields GF (2m), using the concept of extended towers of fields GF (22m), in this case with quadratic extension. Using field towers improve the calculation of finite fields operations, which is applied in the calculation of bilinear pairings, a main part of identity-based cryptography. The basic concepts of arithmetic in GF (2m) are presented, as well as the construction of operations such as addition, multiplication, and multiplicative inverse in extended binary fields. Similarly, it presents the results of its implemen-tation in a Xilinx FPGA device XV5LX110T, which was developed using VHDL language and the ISE Design Suite System Edition 14.4 too

Implementacion de aritmetica de torres de campos finitos binarios de extension 2

The present work shows the basics of arithmetic of binary finite fields GF (2m), using the concept of extended towers of fields GF (22m), in this case with quadratic extension. Using field towers improve the computation of operations over finite fields, which is applied in the calculation of bilinear pairings, a main part of the identity- based cryptography; we present the basic concepts of arithmetic in GF (2m) and construction of operations addition, multiplication and multiplicative inverse in extended binary fields. Similarly presents the results of the implementation in a Xilinx FPGA device XV5LX110T, developed using VHDL language and tool ISE Design Suite System Edition 13.4En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m) extendidos, usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad. Se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 13.4

Implementación de aritmética de torres de campos finitos binarios de extensión 2 en FPGA

En el presente trabajo se muestran los aspectos básicos de la aritmética de campos finitos binarios GF(2m), extendidos usando el concepto de torres de campos GF(22m), en este caso con extensión 2 o cuadrática. El uso de torres de campos agiliza el cómputo de operaciones en los campos finitos, lo cual es aplicado en el cálculo de emparejamientos bilineales, parte fundamental de la criptografía basada en identidad; se presentan los conceptos básicos de aritmética en GF(2m) y la construcción de las operaciones suma y multiplicación en campos binarios extendidos. De igual manera, se presentan los resultados de la implementación en un dispositivo FPGA XV5LX110T de Xilinx Inc., desarrollada usando lenguaje VHDL y la herramienta ISE Design Suite System Edition 14.4

Cryptographic Pairings

This article appeared as Chapter 9 of the book Topics in Computational Number Theory inspired by Peter L. Montgomery , edited by Joppe W. Bos and Arjen K. Lenstra and published by Cambridge University Press. See https://www.cambridge.org/9781107109353

NTRU software implementation for constrained devices

The NTRUEncrypt is a public-key cryptosystem based on the shortest vector problem. Its main characteristics are the low memory and computational requirements while providing a high security level. This document presents an implementation and optimization of the NTRU public-key cryptosys- tem for constrained devices. Speci cally the NTRU cryptosystem has been implemented on the ATMega128 and the ATMega163 microcontrollers. This has turned in a major e ort in order to reduce the consumption of memory and op- timize the computational resources. The di erent resulting optimizations have been compared and evaluated throught the AVR Studio 4 [1]. The nal outcome has also been compared with other published public-key cryptosystems as RSA or ECC showing the great performance NTRUEncrypt is able to deliver at a surprising very low cost

Cryptographic Pairings: Efficiency and DLP security

This thesis studies two important aspects of the use of pairings in cryptography, efficient algorithms and security. Pairings are very useful tools in cryptography, originally used for the cryptanalysis of elliptic curve cryptography, they are now used in key exchange protocols, signature schemes and Identity-based cryptography. This thesis comprises of two parts: Security and Efficient Algorithms. In Part I: Security, the security of pairing-based protocols is considered, with a thorough examination of the Discrete Logarithm Problem (DLP) as it occurs in PBC. Results on the relationship between the two instances of the DLP will be presented along with a discussion about the appropriate selection of parameters to ensure particular security level. In Part II: Efficient Algorithms, some of the computational issues which arise when using pairings in cryptography are addressed. Pairings can be computationally expensive, so the Pairing-Based Cryptography (PBC) research community is constantly striving to find computational improvements for all aspects of protocols using pairings. The improvements given in this section contribute towards more efficient methods for the computation of pairings, and increase the efficiency of operations necessary in some pairing-based protocol

Efficient Algorithms for Large Prime Characteristic Fields and Their Application to Bilinear Pairings

We propose a novel approach that generalizes interleaved modular multiplication algorithms to the computation of sums of products over large prime fields. This operation has widespread use and is at the core of many cryptographic applications. The method reformulates the widely used lazy reduction technique, crucially avoiding the need for storage and computation of double-precision operations. Moreover, it can be easily adapted to the different methods that exist to compute modular multiplication, producing algorithms that are significantly more efficient and memory-friendly. We showcase the performance of the proposed approach in the computation of multiplication over an extension field $\mathbb{F}_{p^k}$, and demonstrate its impact with a record-breaking implementation for bilinear pairings: a full optimal ate pairing over the popular BLS12-381 curve is computed in under half a millisecond on a 3.2GHz Intel Coffee Lake processor, which is about $1.40\times$ faster than the state-of-the-art