Structural Reliability of AlGaN/GaN High Electron Mobility Transistors

The GaN devices have significant advantages in terms of power density, characteristics and voltage range based on conventional compound semiconductors or Silicon. The aim of this work is to observe and analyze the results of 3D Structural Reliability of AlGaN/GaN HEMT structure. The work is mostly focused on the coupled behavior of Aluminum Gallium-nitride (AlGaN)/ Gallium-nitride (GaN) high-electron- mobility transistors (HEMTs). The modeling have to be performed considering to the various coupled properties like piezo- electric effect, inverse piezoelectric effect, mechanical stress, Joule heating effect etc. The Structural Reliability with modeling of AlGaN/GaN HEMTs is performed using ANSYS and MATLAB simulation software

Buffer Trap Related Knee Walkout and the Effects of Self-Heating in AlGaN/GaN HEMTs

Mixed-mode simulations of a class A amplifier is used to study the DC/RF dispersion commonly observed in AlGaN/GaN based HEMTs. We show that the observed knee walkout at frequencies greater than the emission rates of buffer traps (time constants tae > 1 week) is related to the steady state trap density and spatial location due to the DC operational bias. An increase in the drain bias point and an initial distortion of the RF signal, that is expected to disappear as the device global temperature reduces, is observed when a self-heating model is included. Finally, we propose that a reduction in the DC/RF dispersion is possible with a suitable location and concentration of an acceptor doping in the buffer

Device physics and failure mechanisms of deep submicron gate GaN HEMTs for microwave and millimeter-wave applications

openThis thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs.This thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs

Characterization and Modeling of the Threshold Voltage Instability in p-Gate GaN HEMTs

The p-gate GaN HEMT is a modern power semiconductor transistor capable of overcoming the switching speed limitation of conventional Silicon-based technologies. However, the GaN HEMT is a fairly new technology that still suffers undesired effects that affect its operation. Nowadays, the most prominent effects are the shift and instability of the threshold voltage Vth, caused by capacitive coupling into the gate stack as well as trapping, accumulation, and depletion of carriers. In this study, an experimental characterization of the Vth behavior is executed and subsequently used to develop a physically-based compact model. For this purpose, a custom setup is developed capable of high-resolution transient measurements for pulse lengths ranging from 100 ns up to 100 s. Utilizing the setup, commercially available state-of-the-art p-gate GaN HEMTs are investigated, showing a Vth shift and instability that appears relevant up to the nominal operation. The experimental results show that the drain-source voltage VDS yields a Vth shift, which, when applied for long durations (e.g., during off-state), leads to an additional Vth instability. The gate-source voltage VGS also yields significant Vth instabilities, which correlate with the VDS-induced effects. Furthermore, the driving conditions causing an impact on Vth appear to also correlate with the devices’ short-circuit capability and degradation. However, no available models cover the Vth behavior, which is necessary to predict their impact and reliability concerns. Consequently, a compact model is developed based on the surface potential for the drain path, extended by the conduction mechanisms covering the gate path. Finally, the Vth shift is modeled based on capacitive coupling into the gate, while for the Vth instabilities, a possible implementation is exemplified for the impact of VDS

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Particle-Based Modeling of Reliability for Millimeter-Wave GaN Devices for Power Amplifier Applications

abstract: In this work, an advanced simulation study of reliability in millimeter-wave (mm-wave) GaN Devices for power amplifier (PA) applications is performed by means of a particle-based full band Cellular Monte Carlo device simulator (CMC). The goal of the study is to obtain a systematic characterization of the performance of GaN devices operating in DC, small signal AC and large-signal radio-frequency (RF) conditions emphasizing on the microscopic properties that correlate to degradation of device performance such as generation of hot carriers, presence of material defects and self-heating effects. First, a review of concepts concerning GaN technology, devices, reliability mechanisms and PA design is presented in chapter 2. Then, in chapter 3 a study of non-idealities of AlGaN/GaN heterojunction diodes is performed, demonstrating that mole fraction variations and the presence of unintentional Schottky contacts are the main limiting factor for high current drive of the devices under study. Chapter 4 consists in a study of hot electron generation in GaN HEMTs, in terms of the accurate simulation of the electron energy distribution function (EDF) obtained under DC and RF operation, taking into account frequency and temperature variations. The calculated EDFs suggest that Class AB PAs operating at low frequency (10 GHz) are more robust to hot carrier effects than when operating under DC or high frequency RF (up to 40 GHz). Also, operation under Class A yields higher EDFs than Class AB indicating lower reliability. This study is followed in chapter 5 by the proposal of a novel π-Shaped gate contact for GaN HEMTs which effectively reduces the hot electron generation while preserving device performance. Finally, in chapter 6 the electro-thermal characterization of GaN-on-Si HEMTs is performed by means of an expanded CMC framework, where charge and heat transport are self-consistently coupled. After the electro-thermal model is validated to experimental data, the assessment of self-heating under lateral scaling is considered.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Caracterização, modelação e compensação de efeitos de memória lenta em amplificadores de potência baseados em GAN HEMTS

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as the most compelling technology for the transmission of highpower radio-frequency (RF) signals for cellular mobile communications and radar applications. However, despite their remarkable power capabilities, the deployment of GaN HEMT-based RF power amplifiers (PAs) in the mobile communications infrastructure is often ruled out in favor of alternative siliconbased technologies. One of the main reasons for this is the pervasiveness of nonlinear long-term memory effects in GaN HEMT technology caused by thermal and charge-trapping phenomena. While these effects can be compensated for using sophisticated digital predistortion algorithms, their implementation and model-extraction complexity—as well as the power necessary for their real-time execution—make them unsuitable for modern small cells and large-scale multiple-input multiple-output transceivers, where the power necessary for the linearization of each amplification element is of great concern. In order to address these issues and further the deployment of high-powerdensity high-efficiency GaN HEMT-based RF PAs in next-generation communications and radar applications, in this thesis we propose novel methods for the characterization, modeling, and compensation of long-term memory effects in GaN HEMT-based RF PAs. More specifically, we propose a method for the characterization of the dynamic self-biasing behavior of GaN HEMTbased RF PAs; multiple behavioral models of charge trapping and their implementation as analog electronic circuits for the accurate real-time prediction of the dynamic variation of the threshold voltage of GaN HEMTs; a method for the compensation of the pulse-to-pulse instability of GaN HEMT-based RF PAs for radar applications; and a hybrid analog/digital scheme for the linearization of GaN HEMT-based RF PAs for next-generation communications applications.Os transístores de alta mobilidade eletrónica de nitreto de gálio (GaN HEMTs) são considerados a tecnologia mais atrativa para a transmissão de sinais de radiofrequência de alta potência para comunicações móveis celulares e aplicações de radar. No entanto, apesar das suas notáveis capacidades de transmissão de potência, a utilização de amplificadores de potência (PAs) baseados em GaN HEMTs é frequentemente desconsiderada em favor de tecnologias alternativas baseadas em transístores de silício. Uma das principais razões disto acontecer é a existência pervasiva na tecnologia GaN HEMT de efeitos de memória lenta causados por fenómenos térmicos e de captura eletrónica. Apesar destes efeitos poderem ser compensados através de algoritmos sofisticados de predistorção digital, estes algoritmos não são adequados para transmissores modernos de células pequenas e interfaces massivas de múltipla entrada e múltipla saída devido à sua complexidade de implementação e extração de modelo, assim como a elevada potência necessária para a sua execução em tempo real. De forma a promover a utilização de PAs de alta densidade de potência e elevada eficiência baseados em GaN HEMTs em aplicações de comunicação e radar de nova geração, nesta tese propomos novos métodos de caracterização, modelação, e compensação de efeitos de memória lenta em PAs baseados em GaN HEMTs. Mais especificamente, nesta tese propomos um método de caracterização do comportamento dinâmico de autopolarização de PAs baseados em GaN HEMTs; vários modelos comportamentais de fenómenos de captura eletrónica e a sua implementação como circuitos eletrónicos analógicos para a previsão em tempo real da variação dinâmica da tensão de limiar de condução de GaN HEMTs; um método de compensação da instabilidade entre pulsos de PAs baseados em GaN HEMTs para aplicações de radar; e um esquema híbrido analógico/digital de linearização de PAs baseados em GaN HEMTs para comunicações de nova geração.Programa Doutoral em Telecomunicaçõe

O impacto dos efeitos da memória de longo termo na linearizabilidade de amplificadores de potência baseados em AlGaN/GaN HEMT

AlGaN/GaN High Electron Mobility Transistor (HEMT)s are among the preferred options for radio-frequency power amplification in cellular base station transmitters and radar applications. However, despite their promising outlook, the pervasiveness of trapping effects makes them resilient to conventional digital predistortion schemes, which not only decrease their current range of applications but could also preclude their integration in future small cells and multiple-input multiple-output architectures where simpler predistortion schemes are mandatory. So, this PhD thesis aims at developing a meaningful link between the device physics and the linearizability of the AlGaN/GaN HEMT-based Power Amplifier (PA). In order to bridge this gap, this thesis begins with a clear explanation for the mechanisms governing the dominant source of trapping effects in standard AlGaN/GaN HEMTs, namely buffer traps. Based on this knowledge, we explain why the best known physically-supported trapping models, used to represent these devices, are insufficient and present a possible improvement to what we consider to be the most accurate model, supported by Technology Computer-Aided Design (TCAD) simulations. This has also been corroborated through a novel double-pulse technique able to describe experimentally both the capture and emission transients in a wide temporal span under guaranteed isothermal conditions. The measured stretched capture transients validated our understanding of the process while the temperature dependence of the emission profiles confirmed buffer traps as the dominant source of trapping effects. Finally, through both simulations and experimental results, we elaborate here the relationship between the emission time constant and the achievable linearity of GaN HEMT-based PAs, showing that the worst-case scenario happens when the emission time constant is on the order of the time between consecutive envelope peaks above a certain amplitude threshold. This is the case in which we observed a more pronounced hysteresis on the gain and phase-shift characteristics, and so, a stronger impact of the memory effects. The main outcome of this thesis suggests that the biggest linearizability concern in standard AlGaN/GaN HEMT-based PAs lies on the large emission time constants of buffer traps.AlGaN/GaN HEMTs estão entre as opções preferidas para amplificação de potência de radiofrequência em transmissores de estacão base celular e aplicações de radar. No entanto, apesar de sua perspetiva promissora, a influência dos efeitos de defeitos com níveis profundos torna-os imunes aos esquemas convencionais de pre-distorção digital. Assim, esta tese de doutoramento visa desenvolver uma ligação significativa entre a física do dispositivo e a linearização de amplificadores de potência baseados em Al- GaN/GaN HEMTs. Por forma a preencher esta lacuna, esta tese começa com uma explicação clara dos mecanismos que governam a fonte dominante de efeitos de defeitos com níveis profundos em AlGaN/GaN HEMTs standard, especificamente defeitos no buffer. Com base neste conhecimento, são aparentadas as falhas dos modelos físicos mais conhecidos de defeitos de nível profundo usados para representar estes dispositivos, assim como uma possível melhoria suportada em simulações de TCAD. Isto é também corroborado por uma nova técnica de duplo-pulso capaz de descrever experimentalmente os transientes de captura e emissão num amplo intervalo temporal sob condições isotérmicas. Os transientes de captura medidos validam a nossa compreensão do processo, enquanto que a dependência da temperatura nos perfis de emissão confirmou os defeitos no buffer como a fonte dominante de efeitos de defeitos com níveis profundos. Por fim, através de simulações e resultados experimentais, elabora-se aqui a relação entre a constante de tempo de emissão e a linearizabilidade dos amplificadores baseados em AlGaN/GaN HEMT, mostrando que o pior cenário acontece quando a constante de tempo de emissão é da mesma ordem do tempo entre picos consecutivos da envolvente acima de um certo limiar de amplitude. Este é o caso para o qual se observa uma histerese mais pronunciada nas características de ganho e fase e, consequentemente, um impacto mais forte dos efeitos de memória. O resultado principal desta tese sugere que a maior preocupação na linearização de amplificadores baseados em AlGaN/GaN HEMTs standard está nas grandes constantes de tempo de emissão dos defeitos no buffer.Programa Doutoral em Engenharia Eletrotécnic

Advanced GaN HEMTs for high performance microwave power amplifiers

The ever increasing demand for high power levels at higher frequencies from the industry has stimulated extensive research in gallium nitride (GaN) transistor technology over the past two decades. This has led to significant advances of the technology, but the degradation in the device performance due to device self-heating and trap generation in the device epilayers during device operation is still a major challenge with the current GaN high electron mobility transistor (HEMT) technology. This thesis focuses on minimising device self-heating effects by means of efficient heat distribution within the device. Two approaches are analysed in this work. Firstly, the impact on the device DC performance of improved wafer growth conditions by using method called hot-wall MOCVD (metal organic chemical vapour deposition) are investigated. It was found that 2 µm × 100 µm devices on this wafer exhibit only 4% degradation in the saturated output current density at 20 V compared with 13% for devices fabricated on a wafer grown by standard MOCVD growth. This improved performance was attributed to lower thermal boundary resistance achieved by improved growth quality of the epitaxial material layers. In the second approach, the impact on self-heating was investigated through the use of a distributed device channel, i.e. introducing inactive regions along the device channel to distribute the hot spots in the device. Here a planar isolation method was used to achieve planar distributed gate devices that led to low leakage currents below 200 nA/mm at gate voltage of -20 V. A decrease in the peak channel temperature of 30°C was found through thermal simulations over a single 100 µm wide gate finger. Moreover, these distributed channel devices with gate periphery of 10 ×100 µm showed 13 % higher saturated current density than standard devices with the same active device area. The other major issue addressed in this thesis is the so-called current collapse which is a degradation in the output current caused by electron trapping in the device structure. An alternative solution to the conventionally used dielectric passivation is proposed and it entails the use of a thick undoped GaN cap layer to reduce the surface effects by moving the surface further away from the device channel. Drain lag measurements show 15% and 35% decrease in the current at quiescent bias decrease points of [-7 V; 10 V] and [-7 V; 20 V] respectively for the proposed structure compared with 80% decrease and complete current collapse at these quiescent bias points in the same geometry devices on a standard wafer with 2 nm GaN cap layer and a thin 10 nm thin SiNx passivation, respectively. The 10 nm thin passivation layer does not minimise the surface effects, but it protects the devices from oxidation. Finally, a single stage class A amplifier was demonstrated using the developed technology exhibiting peak output power of 30 dBm at 10 GHz and associated power added efficiency of 44% and gain of 10 dB. Also, gain of at least 9.4 dB was shown over 8-13 GHz bandwidth