FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems

Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided in frames and each one has to be completely processed before the next frame arrives. Recently a new method for computing convolutions based on the neuro-inspired philosophy of spiking systems (Address-Event-Representation systems, AER) is achieving high performances. In this paper we present two FPGA implementations of AERbased convolution processors that are able to work with 64x64 images and programmable kernels of up to 11x11 elements. The main difference is the use of RAM for integrators in one solution and the absence of integrators in the second solution that is based on mapping operations. The maximum equivalent operation rate is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Junta de Andalucía P06-TIC-0141

On the AER Convolution Processors for FPGA

Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided into frames and each one has to be completely processed before the next frame arrives in order to warranty the real-time. A spike-based philosophy for computing convolutions based on the neuro-inspired Address-Event- Representation (AER) is achieving high performances. In this paper we present two FPGA implementations of AER-based convolution processors for relatively small Xilinx FPGAs (Spartan-II 200 and Spartan-3 400), which process 64x64 images with 11x11 convolution kernels. The maximum equivalent operation rate that can be reached is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed.Ministerio de Ciencia e Innovación TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Junta de Andalucía P06-TIC-0141

Foreign technology summary of flight crucial flight control systems

A survey of foreign technology in flight crucial flight controls is being conducted to provide a data base for planning future research and technology programs. Only Free World countries were surveyed, and the primary emphasis was on Western Europe because that is where the most advanced technology resides. The survey includes major contemporary systems on operational aircraft, R&D flight programs, advanced aircraft developments, and major research and technology programs. The information was collected from open literature, personal communications, and a tour of several companies, government organizations, and research laboratories in the United Kingdom, France, and the Federal Republic of Germany. A summary of the survey results to date is presented

Progress of analog-hybrid computation

Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging technique

Reports on Hybrid-computer Hardware

Hybrid computer and differential analyzer design and development for university instruction progra

An Efficient behavioral description frontend tool for mixed-mode SPICE simulation

Postprint (published version

Decoders for MST radars

Decoding techniques and equipment used by MST radars are described and some recommendations for new systems are presented. Decoding can be done either by software in special-purpose (array processors, etc.) or general-purpose computers or in specially designed digital decoders. Both software and hardware decoders are discussed and the special case of decoding for bistatic radars is examined

F100 multivariable control synthesis program: Evaluation of a multivariable control using a real-time engine simulation

The design, evaluation, and testing of a practical, multivariable, linear quadratic regulator control for the F100 turbofan engine were accomplished. NASA evaluation of the multivariable control logic and implementation are covered. The evaluation utilized a real time, hybrid computer simulation of the engine. Results of the evaluation are presented, and recommendations concerning future engine testing of the control are made. Results indicated that the engine testing of the control should be conducted as planned

Mechanization of and experience with a triplex fly-by-wire backup control system

A redundant three-axis analog control system was designed and developed to back up a digital fly-by-wire control system for an F-8C airplane. Forty-two flights, involving 58 hours of flight time, were flown by six pilots. The mechanization and operational experience with the backup control system, the problems involved in synchronizing it with the primary system, and the reliability of the system are discussed. The backup control system was dissimilar to the primary system, and it provided satisfactory handling through the flight envelope evaluated. Limited flight tests of a variety of control tasks showed that control was also satisfactory when the backup control system was controlled by a minimum-displacement (force) side stick. The operational reliability of the F-8 digital fly-by-wire control system was satisfactory, with no unintentional downmodes to the backup control system in flight. The ground and flight reliability of the system's components is discussed